X9251TB24 XICOR [Xicor Inc.], X9251TB24 Datasheet - Page 6

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X9251TB24

Manufacturer Part Number
X9251TB24
Description
Quad Digitally-Controlled (XDCP) Potentiometer
Manufacturer
XICOR [Xicor Inc.]
Datasheet
X9251
PRINCIPLES OF OPERATION
The X9251 is an integrated circuit incorporating four
DCPs and their associated registers and counters, and
a serial interface providing direct communication
between a host and the potentiometers.
DCP Description
Each DCP is implemented with a combination of
resistor elements and CMOS switches. The physical
ends of each DCP are equivalent to the fixed terminals
of a mechanical potentiometer (R
RW pin is an intermediate node, equivalent to the
wiper terminal of a mechanical potentiometer.
Figure 1. Detailed Potentiometer Block Diagram
REV 1.3.3 2/10/04
One of Four Potentiometers
#: 0, 1, 2, or 3
IF WCR = 00[H] then R
IF WCR = FF[H] then R
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
W
W
is closet to R
is closet to R
H
DR#0
DR#2
and R
L
H
L
pins). The
8
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MODIFIED SCK
DR#1
DR#3
The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Counter Register
(WCR).
Power Up and Down Recommendations.
There are no restrictions on the power-up or power-
down conditions of V
potentiometer pins provided that V
positive than or equal to V
V
effect.
L
, V
UP/DN
8
W
. The V
SERIAL
BUS
INPUT
UP/DN
CLK
BUS
INPUT
PARALLEL
REGISTER
COUNTER
INC/DEC
(WCR#)
CC
WIPER
LOGIC
Characteristics subject to change without notice.
ramp rate specification is always in
CC
and the voltages applied to the
H
COUNTER
DECODE
, V
- - -
L
, and V
CC
W
CORE
is always more
, i.e., V
DCP
CC
R
R
R
6 of 25
≥ V
H
W
L
H
,

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