DSP56F801PB MOTOROLA [Motorola, Inc], DSP56F801PB Datasheet - Page 22

• Manufacturer Part Number: DSP56F801PB
• Description: 16-bit Digital Signal Processor
• Manufacturer: MOTOROLA [Motorola, Inc]

Operating Conditions:
3.5.4
Operating Conditions:
An internal relaxation oscillator can supply the reference frequency when an external frequency source or
crystal are not used. During a DSP56F801 boot or reset sequence, the relaxation oscillator is enabled by
default, and the PRECS bit in the PLLCR word is set to 0
the relaxation oscillator can be deselected instead by setting the PRECS bit in the PLLCR to 1. When this
occurs, the PRECSS bit in the PLLSR (prescaler clock select status register) data word also sets to 1. If a
changeover between internal and external oscillators is required at startup, internal device circuits
compensate for any asynchronous transitions between the two clock signals so that no glitches occur in the
resulting master clock to the chip. When changing clocks, the user must ensure that the clock source is not
switched until the desired clock is enabled and stable.
To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator
can be incrementally adjusted to within
IOSCTL (internal oscillator control) word allow the user to set in an additional offset (trim) to this preset
value to increase or decrease capacitance. The default value of this trim is 128 units, making the power-up
default capacitor size 432 units. Each unit added or deleted changes the output frequency by about 0.23%,
allowing incremental adjustment until the desired frequency accuracy is achieved.
22
Frequency Accuracy
Frequency Drift over Temp
Frequency Drift over Supply
Trim Range
Trim Accuracy
External reference crystal frequency for the PLL
PLL output frequency
PLL stabilization time
PLL stabilization time
1.
1.
correctly. The PLL is optimized for 8 MHz input crystal.
2.
in the User Manual.
3.
Over full temperature range.
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
ZCLK may not exceed 80 MHz. For additional information on ZCLK and F
This is the minimum time required after the PLL setup is changed to ensure reliable operation.
Use of On-Chip Relaxation Oscillator
Characteristic
Characteristic
1
3
2
3
-40
(F
0
V
V
Table 24. Relaxation Oscillator Characteristics
o
out
SS
SS
o
to +85
/2)
= V
to 0
= V
SSA
SSA
o
C
o
C
= 0 V, V
= 0 V, V
DSP56F801 Preliminary Technical Data
Table 23. PLL Timing
DD
DD
25% of 8 MHz by trimming an internal capacitor. Bits 0-7 of the
= V
= V
Symbol
1
DDA
DDA
f/ t
f/ t
f
T
f
f
T
= 3.0–3.6 V, T
= 3.0–3.6 V, T
Symbol
f
t
t
f
osc
plls
plls
op
(Section
Min
—
—
—
—
7
A
A
= –40 to +85 C
= –40 to +85 C
Min
3.5). If an external oscillator is connected,
40
—
—
6
out
+0.25
+0.1
Typ
0.1
/2, please refer to the OCCS chapter
+2
8
Typ
100
10
—
8
Max
+5
—
—
—
9
Max
200
10
80
—
MOTOROLA
%/
MHz
Unit
%/V
MHz
MHz
Unit
%
%
ms
ms
o
C