SAA7108AE PHILIPS [NXP Semiconductors], SAA7108AE Datasheet - Page 19

• Manufacturer Part Number: SAA7108AE
• Description: HD-CODEC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
8.1
To activate the reset a pulse at least of 2 crystal clocks
duration is required.
During reset (RESET = LOW) plus an extra 32 crystal
clock periods, FSVGC, VSVGC, CBO, HSVGC and
TTX_SRES are set to input mode and HSM_CSYNC and
VSM are set to 3-state. A reset also forces the I
interface to abort any running bus transfer and sets it into
receive condition.
After reset, the state of the I/Os and other functions is
defined by the strapping pins until an I
redefines the corresponding registers; see Table 2.
Table 2 Strapping pins
8.2
The input formatter converts all accepted PD input data
formats, either RGB or Y-C
RGB or Y-C
When double-edge clocking is used, the data is internally
split into portions PPD1 and PPD2. The clock edge
assignment must be set according to the I
bits SLOT and EDGE for correct operation.
2004 Jun 29
FSVGC (pin G1)
VSVGC (pin F1)
CBO (pin G3)
HSVGC (pin E3)
TTXRQ_XCLKO2
(pin C4)
HD-CODEC
Reset conditions
Input formatter
PIN
B
-C
R
data stream.
LOW NTSC M encoding, PIXCLK
HIGH PAL B/G encoding, PIXCLK
LOW 4 : 2 : 2 Y-C
HIGH 4 : 4 : 4 RGB graphics input
LOW input demultiplex phase:
HIGH input demultiplex phase:
LOW input demultiplex phase:
HIGH input demultiplex phase:
LOW slave (FSVGC, VSVGC and
HIGH master (FSVGC, VSVGC
TIED
B
fits to 640
input
fits to 640
input
input (format 0)
(format 3)
LSB = LOW
LSB = HIGH
MSB = LOW
MSB = HIGH
HSVGC are inputs, internal
colour bar is active)
and HSVGC are outputs)
-C
R
, to a common internal
2
PRESET
C-bus access
B
480 graphics
480 graphics
-C
2
C-bus control
R
graphics
2
C-bus
19
If Y-C
the output of the input formatter can be used directly to
feed the video encoder block.
The horizontal upscaling is supported via the input
formatter. According to the programming of the pixel clock
dividers (see Section 8.10), it will upsample the data
stream to 1 , 2
interpolation filter is available. The clock domain transition
is handled by a 4 entries wide FIFO which gets initialized
every field or explicitly at request. A bypass for the FIFO is
available, especially for high input data rates.
8.3
The three 256-byte RAMs of this block can be addressed
by three 8-bit wide signals, thus it can be used to build any
transformation, e.g. a gamma correction for RGB signals.
In the event that the indexed colour data is applied, the
RAMs are addressed in parallel.
The LUTs can either be loaded by an I
or can be part of the pixel data input through the PD port.
In the latter case, 256
expected at the beginning of the input video line, two lines
before the line that has been defined as first active line,
until the middle of the line immediately preceding the first
active line. The first 3 bytes represent the first RGB LUT
data, and so on.
8.4
A 32
map of the cursor can be uploaded by an I
access to specific registers or in the pixel data input via the
PD port. In the latter case the 256 bytes defining the cursor
bit map (2 bits per pixel) are expected immediately
following the last RGB LUT data in the line preceding the
first active line.
The cursor bit map is set up as follows: each pixel
occupies 2 bits. The meaning of these bits depends on the
CMODE I
Transparent means that the input pixels are passed
through, the ‘cursor colours’ can be programmed in
separate registers.
The bit map is stored with 4 pixels per byte, aligned to the
least significant bit. So the first pixel is in bits 0 and 1, the
next pixel in bits 3 and 4 and so on. The first index is the
column, followed by the row; index 0,0 is the upper left
corner.
B
-C
RGB LUT
Cursor insertion
32 dots cursor can be overlaid as an option; the bit
R
2
C-bus register as described in Table 5.
is being applied as a 27 Mbyte/s data stream,
SAA7108AE; SAA7109AE
or 4
3 bytes for the R, G and B LUT are
the input data rate. An optional
Product specification
2
C-bus write access
2
C-bus write