CY8C5246LTI-029 CYPRESS [Cypress Semiconductor], CY8C5246LTI-029 Datasheet - Page 49

• Manufacturer Part Number: CY8C5246LTI-029
• Manufacturer: CYPRESS [Cypress Semiconductor]

8.7.1 Current DAC
The IDAC can be configured for the ranges 0 to 32 µA, 0 to 256
µA, and 0 to 2.048 mA. The IDAC can be configured to source
or sink current.
8.7.2 Voltage DAC
For the VDAC, the current DAC output is routed through
resistors. The two ranges available for the VDAC are 0 to
1.024 V and 0 to 4.096 V. In voltage mode any load connected
to the output of a DAC should be purely capacitive (the output of
the VDAC is not buffered).
9. Programming, Debug Interfaces,
The Cortex-M3 has internal debugging components, tightly
integrated with the CPU, providing the following features:
PSoC devices include extensive support for programming,
testing, debugging, and tracing both hardware and firmware.
JTAG and SWD support all programming and debug features of
the device. The SWV and TRACEPORT provide trace output
from the DWT, ETM, and ITM. TRACEPORT is faster but uses
more pins. SWV is slower but uses only one pin.
Cortex-M3 debug and trace functionality enables full device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE software provides fully integrated
programming and debug support for PSoC devices. The low cost
MiniProg3 programmer and debugger is designed to provide full
programming and debug support of PSoC devices in conjunction
with the PSoC Creator IDE. PSoC interfaces are fully compatible
with industry standard third party tools.
Document Number: 001-66236 Rev. **
JTAG or SWD access
FPB block for implementing breakpoints and code patches
DWT block for implementing watchpoints, trigger resources,
and system profiling
ETM for instruction trace
ITM for support of printf-style debugging
Resources
Reference
Source
PRELIMINARY
Figure 8-6. DAC Block Diagram
Scaler
All Cortex-M3 debug and trace modules are disabled by default
and can only be enabled in firmware. If not enabled, the only way
to reenable them is to erase the entire device, clear flash
protection, and reprogram the device with new firmware that
enables them. Disabling debug and trace features, robust flash
protection, and hiding custom analog and digital functionality
inside the PSoC device provide a level of security not possible
with multichip application solutions. Additionally, all device
interfaces can be permanently disabled (Device Security) for
applications concerned about phishing attacks due to a
maliciously reprogrammed device. Permanently disabling
interfaces is not recommended in most applications because the
designer then cannot access the device. Because all
programming, debug, and test interfaces are disabled when
Device Security is enabled, PSoCs with Device Security enabled
may not be returned for failure analysis.
9.1 SWD Interface
SWD is the default debug interface and is always enabled after
any reset, including POR. This means that the two pins used for
SWD (P1.0 and P1.1) should not generally be used for any other
purpose since they always revert to being SWD pins after any
reset.
The SWD interface is the preferred alternative to JTAG, as it
requires only two pins. The SWD clock frequency can be up to
1/3 of the CPU clock frequency.
SWD uses two pins, either two port 1 pins or the USBIO D+ and
D- pins. The SWD pins cannot be used as GPIO. The USBIO
pins are useful for in system programming of USB solutions that
would otherwise require a separate programming connector.
One pin is used for the data clock and the other is used for data
input and output. SWD can be enabled on only one of the pin
pairs at a time. SWD is used for debugging or for programming
the flash memory. In addition, the SWD interface supports the
SWV trace output if desired.
9.2 JTAG Interface
The IEEE 1149.1 compliant JTAG interface exists on four pins.
The JTAG clock frequency can be up to 8 MHz, or 1/3 of the CPU
clock frequency for 8 and 16-bit transfers, or 1/5 of the CPU clock
frequency for 32-bit transfers, whichever is least. The JTAG
interface is used for programming the flash memory and
debugging.
PSoC
I
I
1x , 8x , 64x
1x , 8x , 64x
source
sink
Range
Range
3R
R
®
5: CY8C52 Family Datasheet
Vout
Iout
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