CY8C5247AXI-051 CYPRESS [Cypress Semiconductor], CY8C5247AXI-051 Datasheet

CY8C5247AXI-051

Manufacturer Part Number

CY8C5247AXI-051

Description

Programmable System-on-Chip (PSoC) DC to 40 MHz operation

Manufacturer

CYPRESS [Cypress Semiconductor]

Datasheet

1.CY8C5247AXI-051.pdf (95 pages)

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General Description

With its unique array of configurable blocks, PSoC

analog, and digital peripheral functions in a single chip. The CY8C52 family offers a modern method of signal acquisition, signal

processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples

(near DC voltages) to ultrasonic signals. The CY8C52 family can handle dozens of data acquisition channels and analog inputs on

every GPIO pin. The CY8C52 family is also a high-performance configurable digital system with some part numbers including inter-

faces such as USB, multimaster I

interfaces, the CY8C52 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM

Cortex™-M3 microprocessor core. Designers can easily create system level designs using a rich library of prebuilt components and

boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C52 family provides unparalleled

opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple

firmware updates.

Features

Cypress Semiconductor Corporation

Document Number: 001-66236 Rev. *A

Notes

1. This feature on select devices only. See

2. GPIOs with opamp outputs are not recommended for use with CapSense.

32-bit ARM Cortex-M3 CPU core

Low voltage, ultra low power

Versatile I/O system

Digital peripherals

DC to 40 MHz operation

Flash program memory, up to 256 KB, 100,000 write cycles,

20-year retention and multiple security features

Up to 64 KB SRAM memory

2-KB electrically erasable programmable read-only memory

(EEPROM) memory, 1 million cycles, and 20 years retention

24-channel direct memory access (DMA) with multilayer

AMBA high-performance bus (AHB) bus access

• Programmable chained descriptors and priorities

• High bandwidth 32-bit transfer support

Operating voltage range: 2.7 V to 5.5 V

High efficiency boost regulator from 1.8-V input to 5.0-V

output

5 mA at 6 MHz

Low power modes including:

• 3-µA sleep mode with real time clock (RTC) and

• 1-µA hibernate mode with RAM retention

28 to 72 I/Os (62 GPIOs, eight SIOs, two USBIOs

Any GPIO to any digital or analog peripheral routability

LCD direct drive from any GPIO, up to 46 × 16 segments

CapSense

1.2 V to 5.5 V I/O interface voltages, up to four domains

Maskable, independent IRQ on any pin or port

Schmitt trigger transistor-transistor logic (TTL) inputs

All GPIOs configurable as open drain high/low, pull up/down,

High-Z, or strong output

25 mA sink on SIO

20 to 24 programmable logic device (PLD) based universal

digital blocks (UDBs)

Full CAN 2.0b 16 RX, 8 TX buffers

Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator

Four 16-bit configurable timer, counter, and PWM blocks

Library of standard peripherals

low-voltage detect (LVD) interrupt

support from any GPIO

C, and controller area network (CAN), a communications protocol. In addition to communication

Ordering Information

[1]

[2]

•

PRELIMINARY

198 Champion Court

Programmable System-on-Chip (PSoC

on page 88 for details.

5 is a true system-level solution providing microcontroller unit (MCU), memory,

[1]

)

[1]

Analog peripherals (2.7 V ≤ V

Programming, debug, and trace

Precision, programmable clocking

Temperature and packaging

PSoC

• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs

• SPI, UART, and I

• Many others available in catalog

Library of advanced peripherals

• Cyclic redundancy check (CRC)

• Pseudo random sequence (PRS) generator

• Local interconnect network (LIN) bus 2.0

• Quadrature decoder

1.024 V ±1% internal voltage reference across –40 °C to

+85 °C (128 ppm/°C)

Successive approximation register (SAR) analog-to-digital

converter (ADC), 12-bit at 1 Msps

One 8-bit, 8-Msps current DAC (IDAC) or 1-Msps voltage

DAC (VDAC)

Two comparators with 95-ns response time

CapSense support

Serial wire debug (SWD) and single-wire viewer (SWV)

interfaces

Cortex-M3 flash patch and breakpoint (FPB) block

Cortex-M3 data watchpoint and trace (DWT) generates data

trace information

Cortex-M3 Instrumentation Trace Macrocell (ITM) can be

used for printf-style debugging

DWT and ITM blocks communicate with off-chip debug and

trace systems via the SWV interface

Bootloader programming supportable through I

UART, USB, and other interfaces

3 to 24 MHz internal oscillator over full temperature and

voltage range

4 to 25 MHz crystal oscillator for crystal PPM accuracy

Internal PLL clock generation up to 40 MHz

32.768 KHz watch crystal oscillator

Low power internal oscillator at 1, 33, and 100 kHz

–40 °C to +85 °C degrees industrial temperature

68-pin QFN and 100-pin TQFP package options

•

San Jose, CA 95134-1709

5: CY8C52 Family Datasheet

DDA

≤ 5.5 V)

•

Revised June 10, 2011

C, SPI,

408-943-2600

)

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