DP8390 NSC [National Semiconductor], DP8390 Datasheet - Page 26

• Manufacturer Part Number: DP8390
• Description: NIC Network Interface Controller
• Manufacturer: NSC [National Semiconductor]

10 0 Internal Registers
10 3 Register Descriptions (Continued)
RECEIVE STATUS REGISTER (RSR)
This register records status of the received packet including information on errors and the type of address match either
physical or multicast The contents of this register are written to buffer memory by the DMA after reception of a good packet If
packets with errors are to be saved the receive status is written to memory at the head of the erroneous packet if an erroneous
packet is received If packets with errors are to be rejected the RSR will not be written to memory The contents will be cleared
when the next packet arrives CRC errors Frame Alignment errors and missed packets are counted internally by the NIC which
relinquishes the Host from reading the RSR in real time to record errors for Network Management Functions The contents of
this register are not specified until after the first reception
Note Following coding applies to CRC and FAE bits
FAE CRC
0
0
1
1
Bit
D0
D1
D2
D3
D4
D5
D6
D7
0 No Error (Good CRC and
1 CRC Error
0 Illegal will not occur
1 Frame Alignment Error and CRC Error
Type of Error
Symbol
MPA
PRX
CRC
PHY
DFR
FAE
DIS
FO
k
6 Dribble Bits)
DFR
7
(Continued)
0CH (READ)
PACKET RECEIVED INTACT Indicates packet received without error (Bits
CRC FAE FO and MPA are zero for the received packet )
CRC ERROR Indicates packet received with CRC error Increments Tally
Counter (CNTR1) This bit will also be set for Frame Alignment errors
FRAME ALIGNMENT ERROR Indicates that the incoming packet did not end
on a byte boundary and the CRC did not match at last byte boundary Increments
Tally Counter (CNTR0)
FIFO OVERRUN This bit is set when the FIFO is not serviced causing overflow
during reception Reception of the packet will be aborted
MISSED PACKET Set when packet intended for node cannot be accepted by
NIC because of a lack of receive buffers or if the controller is in monitor mode
and did not buffer the packet to memory Increments Tally Counter (CNTR2)
PHYSICAL MULTICAST ADDRESS Indicates whether received packet had a
physical or multicast address type
0 Physical Address Match
1 Multicast Broadcast Address Match
RECEIVER DISABLED Set when receiver disabled by entering Monitor mode
Reset when receiver is re-enabled when exiting Monitor mode
DEFERRING Set when CRS or COL inputs are active If the transceiver has
asserted the CD line as a result of the jabber this bit will stay set indicating the
jabber condition
DIS
6
PHY
5
MPA
4
26
FO
3
FAE
2
Description
CRC
1
PRX
0