DP8390 NSC [National Semiconductor], DP8390 Datasheet - Page 37

• Manufacturer Part Number: DP8390
• Description: NIC Network Interface Controller
• Manufacturer: NSC [National Semiconductor]

13 0 Bus Arbitration and Timing
SLAVE MODE TIMING
When CS is low the NIC becomes a bus slave The CPU
can then read or write any internal registers All register
access is byte wide The timing for register access is shown
below The host CPU accesses internal registers with four
address lines
TIME BETWEEN CHIP SELECTS
The NIC requires that successive chip selects be no closer
than 4 bus clocks (BSCK) together below If the condition is
violated the NIC may glitch ACK CPUs that operate from
pipelined instructions (i e 386) or have a cache (i e
RA0–RA3
SRD and SWR strobes
Time between Chip Selects
Read from Register
(Continued)
Write to Register
37
ADS0 is used to latch the address when interfacing to a
multiplexed address data bus Since the NIC may be a local
bus master when the host CPU attempts to read or write to
the controller an ACK line is used to hold off the CPU until
the NIC leaves master mode Some number of BSCK cycles
is also required to allow the NIC to synchronize to the read
or write cycle
486) can execute consecutive I O cycles very quickly The
solution is to delay the execution of consecutive I O cycles
by either breaking the pipeline or forcing the CPU to access
outisde it’s cache
TL F 8582 – A1
TL F 8582 – 74
TL F 8582 – 75