DP8390 NSC [National Semiconductor], DP8390 Datasheet - Page 5

• Manufacturer Part Number: DP8390
• Description: NIC Network Interface Controller
• Manufacturer: NSC [National Semiconductor]

CS
MWR
MRD
SWR
SRD
ACK
RA0–RA3
PRD
WACK
INT
RESET
BREQ
BACK
PRQ ADS1
READY
5 0 Pin Descriptions
BUS INTERFACE PINS (Continued)
Symbol
DIP Pin No
45–48
19
20
21
22
23
24
44
43
42
41
31
30
29
28
Function
(Continued)
O Z
O Z
O Z
O
O
O
O
I
I
I
I
I
I
I
I
CHIP SELECT Chip Select places controller in slave mode for P access to
internal registers Must be valid through data portion of bus cycle RA0 – RA3 are
used to select the internal register SWR and SRD select direction of data
transfer
MASTER WRITE STROBE Strobe for DMA transfers active low during write
cycles (t2 t3 tw) to buffer memory Rising edge coincides with the presence of
valid output data TRI-STATE until BACK asserted
MASTER READ STROBE Strobe for DMA transfers active during read cycles
(t2 t3 tw) to buffer memory Input data must be valid on rising edge of MRD
TRI-STATE until BACK asserted
SLAVE WRITE STROBE Strobe from CPU to write an internal register selected
by RA0– RA3
SLAVE READ STROBE Strobe from CPU to read an internal register selected
by RA0 – RA3
ACKNOWLEDGE Active low when NIC grants access to CPU Used to insert
WAIT states to CPU until NIC is synchronized for a register read or write
operation
REGISTER ADDRESS These four pins are used to select a register to be read
or written The state of these inputs is ignored when the NIC is not in slave mode
(CS high)
PORT READ Enables data from external latch onto local bus during a memory
write cycle to local memory (remote write operation) This allows asynchronous
transfer of data from the system memory to local memory
WRITE ACKNOWLEDGE Issued from system to NIC to indicate that data has
been written to the external latch The NIC will begin a write cycle to place the
data in local memory
INTERRUPT Indicates that the NIC requires CPU attention after reception
transmission or completion of DMA transfers The interrupt is cleared by writing
to the ISR All interrupts are maskable
RESET Reset is active low and places the NIC in a reset mode immediately no
packets are transmitted or received by the NIC until STA bit is set Affects
Command Register Interrupt Mask Register Data Configuration Register and
Transmit Configuration Register The NIC will execute reset within 10 BUSK
cycles
BUS REQUEST Bus Request is an active high signal used to request the bus for
DMA transfers This signal is automatically generated when the FIFO needs
servicing
BUS ACKNOWLEDGE Bus Acknowledge is an active high signal indicating that
the CPU has granted the bus to the NIC If immediate bus access is desired
BREQ should be tied to BACK Tying BACK to V
PORT REQUEST ADDRESS STROBE 1
NOTE This line will power up as TRI-STATE until the Data Configuration
Register is programmed
READY This pin is set high to insert wait states during a DMA transfer The NIC
will sample this signal at t3 during DMA transfers
32-BIT MODE If LAS is set in the Data Configuration Register this line is
programmed as ADS1 It is used to strobe addresses A16 – A31 into external
latches (A16– A31 are the fixed addresses stored in RSAR0 RSAR1 ) ADS1
will remain at TRI-STATE until BACK is received
16-BIT MODE If LAS is not set in the Data Configuration Register this line is
programmed as PRQ and is used for Remote DMA Transfers In this mode
PRQ will be a standard logic output
5
Description
CC
will result in a deadlock