DP8390 NSC [National Semiconductor], DP8390 Datasheet - Page 52

• Manufacturer Part Number: DP8390
• Description: NIC Network Interface Controller
• Manufacturer: NSC [National Semiconductor]

15 0 Switching Characteristics
Note 1 All bits entering NIC must be properly decoded if the PLL is still locking the clock to the NIC should be disabled or CRS delayed Any two sequential 1 data
bits will be interpreted as Synch
Note 2 This is a minimum requirement which allows reception of a packet
Note 1 The NIC requires a minimum number of receive clocks following the de-assertion of carrier sense (CRS) These additional clocks are provided by the
DP8391 SNI If other decoder PLLs are being used additional clocks should be provided Short clocks or glitches are not allowed
Note 2 Up to 5 bits of dribble bits can be tolerated without resulting in a receive error
Note 3 Guarantees to only load bit N additional bits up to tdrb can be tolerated
Note 4 This is the time required for the receive state machine to complete end of receive processing This parameter is not measured but is guaranteed by design
This is not a measured parameter but is a design requirement
Note 5 CRS must remain de-asserted for a minimum of 2 RXC cycles to be recognized as end of carrier
Symbol
rxrck
tdrb
tifg
tcrsl
Symbol
rch
rcl
rcyc
rds
rdh
pts
Minimum Number of Receive Clocks
after CRS Low (Note 1)
Maximum of Allowed Dribble Bits Clocks
(Note 2)
Receive Recovery Time
(Notes 4 5)
Receive Clock to Carrier Sense Low
(Note 3)
Receive Clock High Time
Receive Clock Low Time
Receive Clock Cycle Time
Receive Data Setup Time to
Receive Clock High (Note 1)
Receive Data Hold Time from
Receive Clock High
First Preamble Bit to Synch
(Note 2)
Parameter
Serial Timing Receive (Beginning of Frame)
Parameter
Serial Timing Receive (End of Frame)
(Continued)
52
Min
40
40
80
20
17
8
Min
5
0
Max
120
Max
40
3
1
cycles
TL F 8582– 88
Units
TL F 8582– 89
rcyc
cycles
cycles
cycles
cycles
Units
ns
ns
ns
ns
ns
rcyc
rcyc
rcyc
rcyc