NHPXA270CXXX INTEL [Intel Corporation], NHPXA270CXXX Datasheet
NHPXA270CXXX
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NHPXA270CXXX Summary of contents
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Intel® PXA270 Processor Electrical, Mechanical, and Thermal Specification High-performance processor: n — Intel XScale® microarchitecture with Intel® Wireless MMX™ Technology — 7 Stage pipeline — instruction cache — data cache — “mini” data cache ...
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY ...
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Contents 1 Introduction .........................................................................................................1-1 1.1 About This Document.................................................................................1-1 1.1.1 1.1.2 1.1.3 2 Functional Overview ...........................................................................................2-1 3 Package Information...........................................................................................3-1 3.1 Package Information ..................................................................................3-1 3.2 Processor Materials....................................................................................3-6 3.3 Junction To Case Temperature Thermal Resistance .................................3-7 3.4 Processor Markings....................................................................................3-7 3.5 Tray Drawing ..............................................................................................3-8 ...
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Intel® PXA270 Processor Contents 6.2.7 6.2.8 6.2.9 6.2.10 Voltage-Change Timing...............................................................6-11 6.3 GPIO Timing Specifications .....................................................................6-11 6.4 Memory and Expansion-Card Timing Specifications................................6-12 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.5 LCD Timing Specifications .......................................................................6-43 6.6 SSP Timing Specifications .......................................................................6-44 6.7 JTAG ...
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Non-burst ROM, SRAM, or Flash Read Timing .....................................6-20 6-12 32-Bit Burst-of-Eight ROM or Flash Read Timing ............................................6-21 6-13 Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash Timing..........6-22 6-14 16-bit ROM/Flash/SRAM Read for 4/2/1 Bytes Timing ....................................6-23 6-15 ...
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Intel® PXA270 Processor Contents 6-5 GPIO Reset Timing Specifications .....................................................................6-6 6-6 Sleep-Mode Timing Specifications .....................................................................6-7 6-7 Deep-Sleep Mode Timing Specifications ...........................................................6-8 6-8 GPIO Pu/Pd Timing Specifications for Deep-Sleep Mode .................................6-9 6-9 Standby-Mode Timing Specifications ...............................................................6-10 6-10 Idle-Mode Timing Specifications ......................................................................6-10 ...
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Revision History §§ Date April 2004 June 2004 Electrical, Mechanical, and Thermal Specification Revision -001 First public release of the EMTS -002 Added 23x23 mm 360-ball PBGA package Intel® PXA270 Processor Contents Description vii ...
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Intel® PXA270 Processor Contents viii Electrical, Mechanical, and Thermal Specification ...
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Introduction The Intel® PXA270 processor (PXA270 processor) provides industry-leading multimedia performance, low-power capabilities, rich peripheral integration and second generation memory stacking. Designed from the ground up for wireless clients, it incorporates the latest Intel advances in mobile technology over its ...
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Intel® PXA270 Processor Introduction Single-bit items have either of two states: • clear — the item contains the value 0b0. To clear a bit, write 0b0 to it. • set — the item contains the value 0b1. To set a ...
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Functional Overview The Intel® PXA270 processor is an integrated system-on-a-chip microprocessor for high performance, dynamic, low-power portable handheld and hand-set devices as well as embedded platforms. It incorporates the Intel XScale® technology which complies with the ARM* version 5TE instruction ...
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Intel® PXA270 Processor Functional Overview Figure 2-1. Intel® PXA270 Processor Block Diagram, Typical System RTC RTC OS Timers OS Tim ers 4 x PWM 4 x PWM Interrupt Interrupt Controller C ontrolle SSP 3 x SSP USIM ...
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Package Information This chapter provides the mechanical specifications for the PXA270 processor. The PXA270 processor is offered in two packages. The 13- by 13-mm, 356-ball, 0.50-mm VF- BGA molded matrix array package is shown in 23-mm, 360-ball, 1.0-mm PBGA molded ...
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Intel® PXA270 Processor Package Information Note: Figure 3-2 and Figure 3-3 Figure 3-2. 13x13mm VF-BGA Intel® PXA270 Processor Package, bottom view A B 3-2 show all dimensions in millimeters (mm ø0.30±0.05 (356) ...
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Figure 3-3. 13x13mm VF-BGA Intel® PXA270 Processor Package, side view C Figure 3-4. VF-BGA Product Information Decoder R Package Type LV=Leaded RC=Lead-Free Intel XScale® Family Product Family Member 270=Discrete product Electrical, Mechanical, and Thermal Specification SEATING PLANE ...
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Intel® PXA270 Processor Package Information Note: Figure 3-5, Figure 3-6 Figure 3-5. 23x23 mm PBGA Intel® PXA270 Processor Package (Top View) A1 CORNER Figure 3-6. 23x23 mm PBGA Intel® PXA270 Processor Package (Bottom View) 1.00 1.00 3-4 and Figure 3-7 ...
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Figure 3-7. 23x23 mm PBGA Intel® PXA270 Processor Package (Side View) Figure 3-8. PBGA Product Information Decoder F Package Type FW = Leaded NH = Lead-Free Intel XScale® Family Product Family Member 270 = Discrete product Electrical, Mechanical, and Thermal ...
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Intel® PXA270 Processor Package Information 3.2 Processor Materials Figure 3-9. 13x13mm VF-BGA Intel® PXA270 Processor Package, bottom view Table 3-1 describes the basic material properties of the processor components. 3-6 Electrical, Mechanical, and Thermal Specification ...
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Table 3-1. Processor Material Properties Component Mold compound Solder balls † Subsequent processor steppings may use 3.3 Junction To Case Temperature Thermal Resistance Parameter Theta Jc 3.4 Processor Markings The diagram in this section details the processor’s top markings, which ...
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Intel® PXA270 Processor Package Information 3.5 Tray Drawing For tray drawing information, refer to the Intel Developer website for the Intel® Wireless Communications and Computing Package Users Guide. 3-8 §§ Electrical, Mechanical, and Thermal Specification ...
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Pin Listing and Signal Definitions This chapter describes the signals and pins for the Intel® PXA270 processor. For descriptions of all PXA270 processor signals, refer to the “System Architecture” chapter in the Intel® PXA27x Processor Family Developer’s Manual. Table 4-2 ...
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Intel® PXA270 Processor Pin Listing and Signal Definitions 4.1 Ball Map View Note: In the following ball map figures the lowercase letter “n”, which normally indicates negation, appears as uppercase “N”. 4.1.1 13x13 mm VF-BGA Ball map Figure 4-1 through ...
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Figure 4-2. 13x13 mm VF-BGA Ball Map, Top View (upper right quarter GPIO<113> GPIO<28> GPIO<37> VCC_IO GPIO<29> GPIO<38> GPIO<26> GPIO<23> GPIO<30> GPIO<36> GPIO<27> GPIO<17> GPIO<22> GPIO<40> VSS_IO GPIO<25> VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE ...
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Intel® PXA270 Processor Pin Listing and Signal Definitions Figure 4-3. 13x13 mm VF-BGA Ball Map, Top View (bottom left quarter) N MD<27> MD<28> MD<12> P VCC_MEM MD<11> MD<26> R MD<24> VSS_MEM MD<25> T MD<23> VCC_CORE MD<8> U MD<7> VCC_MEM VSS_CORE ...
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Figure 4-4. 13x13 mm VF-BGA Ball Map, Top View (bottom right quarter) VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_BB GPIO<54> VSS_CORE VSS_IO GPIO<50> GPIO<53> GPIO<106> GPIO<105> GPIO<102> GPIO<48> GPIO<52> GPIO<107> GPIO<103> GPIO<101> GPIO<100> GPIO<51> GPIO<108> GPIO<104> VCC_CORE ...
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Intel® PXA270 Processor Pin Listing and Signal Definitions 4.1.2 23x23 mm PBGA Ball map Figure 4-5. 23x23 mm PBGA Ball Map, Top View (Upper Left Quarter VSS_MEM VSS_MEM B VSS_MEM VCC_MEM C MA[16] MA[17] D MA[14] MA[15] E ...
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Figure 4-6. 23x23 mm PBGA Ball Map, Top View (Upper Right Quarter GPIO[22] GPIO[38] GPIO[26] VSS_IO GPIO[36] GPIO[24] GPIO[40] GPIO[27] GPIO[16] GPIO[28] GPIO[37] VCC_IO VSS_CORE VCC_CORE VSS_CORE VCC_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE ...
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Intel® PXA270 Processor Pin Listing and Signal Definitions Figure 4-7. 23x23 mm PBGA Ball Map, Top View (Lower Left Quarter) M MD[13] MD[11] N MD[28] MD[26] P MD[27] VSS_MEM R MD[10] MD[23] T MD[9] VSS_MEM U MD[22] V MD[20] VSS_MEM ...
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Figure 4-8. 23x23 mm PBGA Ball Map, Top View (Lower Right Quarter) VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VCC_CORE VSS_CORE VCC_CORE VSS_CORE BOOT_SEL GPIO[50] GPIO[106] GPIO[104] GPIO[52] GPIO[105] GPIO[102] GPIO[53] GPIO[108] VSS_IO GPIO[51] GPIO[54] GPIO[107] 12 ...
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Intel® PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Usage Summary (Sheet 1 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) VCC_MEM D6 A3 MA<25> OCZ C4 C4 MA<24> OCZ D4 E4 MA<23> OCZ C2 D4 ...
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Table 4-1. Pin Usage Summary (Sheet 2 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) ICOC N1 P1 MD<27> Z ICOC P3 N2 MD<26> Z ICOC R3 N4 MD<25> Z ICOC R1 N3 MD<24> Z ICOC T1 R2 ...
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Intel® PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Usage Summary (Sheet 3 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) ICOC U4 T4 MD<5> Z ICOC Y2 U3 MD<4> Z ICOC Y3 Y1 MD<3> Z ...
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Table 4-1. Pin Usage Summary (Sheet 4 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) ICOC AB6 W5 GPIO<20> Z ICOC AD5 Y6 GPIO<21> Z ICOC B6 C7 GPIO<33> Z ICOC A10 D10 GPIO<49> Z ICOC B7 D8 ...
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Intel® PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Usage Summary (Sheet 5 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) ICOC AC14 Y12 GPIO<52> Z ICOC AB14 AA12 GPIO<53> Z ICOC AA14 AB13 GPIO<54> Z ...
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Table 4-1. Pin Usage Summary (Sheet 6 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) ICOC H24 F22 GPIO<61> Z ICOC H22 G22 GPIO<62> Z ICOC H23 J20 GPIO<63> Z ICOC J22 H22 GPIO<64> Z ICOC K24 K20 ...
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Intel® PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Usage Summary (Sheet 7 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) ICOC N22 M20 GPIO<86> Z ICOC N23 M22 GPIO<87> Z VCC_IO ICOC C11 A8 GPIO<11> ...
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Table 4-1. Pin Usage Summary (Sheet 8 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) ICOC C13 B11 GPIO<30> Z ICOC C12 C11 GPIO<31> Z ICOC A20 C16 GPIO<32> Z ICOC A21 B19 GPIO<34> Z ICOC B19 D17 ...
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Intel® PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Usage Summary (Sheet 9 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) ICOC A11 C10 GPIO<47> Z ICOC C23 C22 GPIO<88> Z ICOC D22 C21 GPIO<89> Z ...
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Table 4-1. Pin Usage Summary (Sheet 10 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) GPIO<104 ICOC AD15 W14 > Z GPIO<105 ICOC AB16 Y13 > Z GPIO<106 ICOC AB15 W13 > Z GPIO<107 ICOC AC15 AB14 > ...
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Intel® PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Usage Summary (Sheet 11 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) GPIO<118 ICOC A22 B20 > Z VCC_USB IAOA B22 D18 USBC_P Z IAOA C20 E19 ...
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Table 4-1. Pin Usage Summary (Sheet 12 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) Y23 W22 PWR_EN OC NBATT_F AB24 U19 IC AULT NVDD_F W22 V20 IC AULT ICOC AA24 V21 SYS_EN Z PWR_CA AB21 Y19 OA ...
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Intel® PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Usage Summary (Sheet 13 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) A24 A22 VCC_USB PS A23 B22 VCC_USB PS B23 D19 VCC_USB PS VCC_LC P24 M19 ...
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Table 4-1. Pin Usage Summary (Sheet 14 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) VCC_ME W2 N AD12 AA11 VCC_BB PS AC20 AB19 VCC_PLL PS VCC_SRA VCC_SRA ...
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Intel® PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Usage Summary (Sheet 15 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) VCC_CO N/A R18 PS RE VCC_CO U18 N VCC_CO N/A V15 PS RE ...
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Table 4-1. Pin Usage Summary (Sheet 16 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) VSS_ME VSS_ME AA5 VSS_ME AA8 VSS_ME AA9 VSS_ME D9 AA1 ...
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Intel® PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Usage Summary (Sheet 17 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) VSS_COR G21 VSS_COR D21 VSS_COR D12 ...
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Signal Types Table 4-2. Pin Usage and Mapping Notes Note GPIO reset/deep sleep operation: After any reset is asserted or if the PXA270 processor is in deep sleep mode, these pins are configured as GPIO inputs by default. The ...
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Intel® PXA270 Processor Pin Listing and Signal Definitions Table 4-3. Signal Types Type IC CMOS input OC CMOS output OCZ CMOS output, three-stateable ICOCZ CMOS bidirectional, three-stateable IA Analog input OA Analog output IAOA Analog bidirectional IAOAZ Analog bidirectional - ...
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Table 4-4. Memory Controller Pin Reset Values (Sheet Reset, Sleep, Standby, Deep-Sleep, Frequency Pin Name Change, and Manual Self-Refresh Mode Values nPOE GPIO (memory controller drives high) nPWE GPIO (memory controller drives high) NOTE: † This indicates ...
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Intel® PXA270 Processor Pin Listing and Signal Definitions 4-30 Electrical, Mechanical, and Thermal Specification ...
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Electrical Specifications 5.1 Absolute Maximum Ratings The absolute maximum ratings (shown in stresses. These limits prevent permanent damage to the Intel® PXA270 processor. Note: Absolute maximum ratings are not operating ranges. Table 5-1. Absolute Maximum Ratings Symbol Description T Storage ...
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Intel® PXA270 Processor Electrical Specifications Table 5-2 shows each power domains supported voltages (except for VCC_MEM and VCC_CORE). Table 5-3 ranges (VCC_MEM). (VCC_CORE). The operating temperature specification is a function of voltage and frequency. Table 5-2. Voltage, Temperature, and Frequency ...
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Table 5-2. Voltage, Temperature, and Frequency Electrical Specifications (Sheet Symbol Description Voltage applied on VCC_LCD @2.5V VVCC3b (+10 / -10%) Voltage applied on VCC_LCD @3.0V VVCC3c (+10 / -10%) Voltage applied on VCC_LCD @3.3V VVCC3d (+10 / ...
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Intel® PXA270 Processor Electrical Specifications Table 5-3. Memory Voltage and Frequency Electrical Specifications Symbol Description Memory Voltage and Frequency Range 1 VMEM1 Voltage applied on VCC_MEM External synchronous memory frequency, fSM1A SDCLK1, SDCLK2 External synchronous memory frequency, fSM1B SDCLK0 Tsysramp ...
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Table 5-4. Core Voltage and Frequency Electrical Specifications (Sheet Core Voltage and Frequency Range 2 (91/45.5/91/45.5) and (104/104/104/104) VVCCC2 Voltage applied on VCC_CORE fCORE2 Core operating frequency Tpwrramp Ramp Rate Core Voltage and Frequency Range 3 (156/104/104/104) ...
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Intel® PXA270 Processor Electrical Specifications 5.2.1 Internal Power Domains The external power supplies are used to generate several internal power domains, which are shown in Table 5-5. Refer to the and Power” section of the Intel® PXA27x Processor Family Developers ...
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Table 5-7. Power-Consumption Specifications (Sheet Parameter Description Active Power Consumption 520 MHz Active Power (208 MHz System bus) 416 MHz Active Power (208 MHz System bus) 312 MHz Active Power (208 MHz System bus) 312 MHz Active ...
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Intel® PXA270 Processor Electrical Specifications Table 5-7. Power-Consumption Specifications (Sheet Parameter Description 1 13 MHz Idle Mode Power (LCD off) Deep-Sleep mode Sleep mode Standby mode NOTE MHz Idle Mode (CCCR[CPDIS] =1 (CCCR[PPDIS ...
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Table 5-8. Standard Input, Output, and I/O Pin DC Operating Conditions (Sheet Symbol Description Output high voltage, all standard output and I/ O pins, relative to applicable VCC (VCC_IO, 1 VOH VCC_MEM, VCC_BB, VCC_LCD, VCC_USB, or VCC_USIM) ...
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Intel® PXA270 Processor Electrical Specifications Table 5-9. Typical 32.768-kHz Crystal Requirements (Sheet Parameter Motional capacitance (C Equivalent series resistance (R Insulation resistance at 100 V Aging, at operating temperature per year 5-10 Minimum ) — ...
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Table 5-10. Typical External 32.768-kHz Oscillator Requirements Symbol Description Amplifier Specifications VIH_X Input high voltage, TXTAL_IN VIL_X Input low voltage, TXTAL_IN IIN_XT Input leakage, TXTAL_IN Input capacitance, TXTAL_IN/ CIN_XT TXTAL_OUT tS_XT Stabilization time Board Specifications Parasitic resistance, TXTAL_IN/ RP_XT TXTAL_OUT ...
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Intel® PXA270 Processor Electrical Specifications Table 5-12. Typical External 13.000-MHz Oscillator Requirements Symbol Description Amplifier Specifications VIH_X Input high voltage, PXTAL_IN VIL_X Input low voltage, PXTAL_IN IIN_XP Input leakage, PXTAL_IN CIN_XP Input capacitance, PXTAL_IN/PXTAL_OUT tS_XP Stabilization time Board Specifications Parasitic ...
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Table 5-14. CLK_TOUT Specifications Parameter Jitter Load capacitance (C L Rise and Fall time (Tr & Tf) 5.7 48 MHz Output Specifications Software may configure GPIO<11> or GPIO<12> alternate functions to enable the 48-MHz clock output. The 48-MHz output clock ...
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Intel® PXA270 Processor Electrical Specifications 5-14 Electrical, Mechanical, and Thermal Specification ...
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AC Timing Specifications A pin’s alternating-current (AC) characteristics include input and output capacitance. These factors determine the loading for external drivers and other load analyses. The AC characteristics also include a derating factor, which indicates how much the AC timings ...
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Intel® PXA270 Processor AC Timing Specifications Figure 6-1. AC Test Load 6.2 Reset and Power Manager Timing Specifications The processor asserts the nRESET_OUT pin in one of several different modes: • Power-on reset • Hardware reset • Watchdog reset • ...
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The processor asserts the PWR_EN signal to enable the power supplies VCC_CORE, VCC_SRAM, and VCC_PLL. These supplies can turn on in any order but must all be established within 125 milliseconds of the assertion of PWR_EN. 6. The external ...
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Intel® PXA270 Processor AC Timing Specifications Table 6-2. Power-On Timing Specifications (Sheet 2 of 2)(OSCC[CRI Symbol Description Power-on Ramp Rate for all external high t sysramp -voltage power domains Power-on Ramp Rate for all external low -voltage power ...
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Table 6-4. Hardware Reset Timing Specifications (OSCC[CRI Symbol Description Delay between nRESET asserted and t 6 nRESET_OUT asserted t Assertion time of nRESET 7 Delay between nRESET de-asserted and t 8 nRESET_OUT de-asserted 6.2.3 Watchdog Reset Timing Watchdog ...
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Intel® PXA270 Processor AC Timing Specifications Table 6-5. GPIO Reset Timing Specifications Symbol Description Minimum assert time of GPIO<1> tA_GPIO<1> 13.000-MHz input clock cycles Delay between GPIO<1> asserted and tDHW_OUT_A nRESET_OUT asserted in 13.000-MHz input clock cycles Delay between nRESET_OUT ...
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Figure 6-5. Sleep Mode Timing Intel® PXA27x State: SLEEP (ENTRY) Wakeup Event SYS_EN (High) VCC_USB, VCC_IO, VCC_BB,VCC_MEM, (Enabled) VCC_LCD, VCC_USIM PWR_EN Tentry VCC_CORE, VCC_SRAM, VCC_PLL nVDD_FAULT nRESET_OUT Table 6-6. Sleep-Mode Timing Specifications Symbol Description Delay between MCR sleep command 5 ...
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Intel® PXA270 Processor AC Timing Specifications Figure 6-6. Deep-Sleep-Mode Timing Intel® PXA27x State: DEEP SLEEP (ENTRY) Wakeup Event Tenable SYS_EN VCC_USB, VCC_IO, VCC_BB, VCC_MEM, VCC_LCD, VCC_USIM PWR_EN Tdentry VCC_CORE, VCC_SRAM, VCC_PLL nVDD_FAULT nRESET_OUT Deep-Sleep Command Table 6-7. Deep-Sleep Mode Timing ...
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GPIO states in Deep-Sleep mode If the external high voltage power domains (VCC_IO, VCC_MEM, VCC_BB, VCC_LCD, VCC_USB, VCC_USIM) remain powered on during deep-sleep, the PGSR values are driven onto all the GPIO pins (that are configured as outputs) for ...
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Intel® PXA270 Processor AC Timing Specifications 6.2.7 Standby-Mode Timing Table 6-9. Standby-Mode Timing Specifications Symbol Description — 13M mode to standby mode entry — Standby mode exit to 13M mode — Run mode to standby mode entry — Standby mode ...
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Voltage-Change Timing 2 The PWR I C uses the regular I mode operation is supported). Software controls the time required for initiating the voltage change sequence through completion. The voltage-change timing is a product of the number of commands ...
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Intel® PXA270 Processor AC Timing Specifications 6.4 Memory and Expansion-Card Timing Specifications Interfaces with the following memories must observe the AC timing requirements given in the following subsections: • Section 6.4.1, “Internal SRAM Read/Write Timing Specifications” • Section 6.4.2, “SDRAM ...
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Table 6-15. SDRAM Interface AC Specifications (Sheet 1.8V +20% / –5% Symbols Parameters MIN SDCLK1, SDCLK2 tsdCLK 9.6 period nSDCAS, tsdCMD nSDRAS, nWE, 1 nSDCS assert time nSDCAS to tsdCAS nSDCAS assert 2 time nSDRAS to tsdRCD ...
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Intel® PXA270 Processor AC Timing Specifications Table 6-15. SDRAM Interface AC Specifications (Sheet 1.8V +20% / –5% Symbols Parameters MIN MD<31:0> read data input setup tsdSDIS TBD time from SDCLK<2:1> rise MD<31:0> read data input hold tsdSDIH ...
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Figure 6-7. SDRAM Timing tsdCLK SDCLK<1> SDCKE<1> nop act nop command nSDCS<0> nSDRAS nSDCAS nWE MD<31:0> read MD<31:0> write DQM<3:0> RDnWR Electrical, Mechanical, and Thermal Specification tsdRC tsdCL tsdRP tsdCMD nop read pre nop act tsdRAS tsdRCD tsdSDIS tsdIH 0b0000 ...
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Intel® PXA270 Processor AC Timing Specifications Figure 6-8. SDRAM 4-Beat Read/4-Beat Write, Different Banks Timing SDCLK<1> SDCKE<1> read(0) pre(1) command nSDCS<0> nSDCS<1> nSDRAS nSDCAS col bank MA<24:10> nWE MD<31:0> (read) MD<31:0> (write) DQM<3:0> RDnWR NOTES: 1. MDCNFG[DTC] = 0b00 (CL ...
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Figure 6-9. SDRAM 4-Beat Write/4-Beat Write, Same Bank-Same Row Timing SDCLK<1> SDCKE<1> command nop nSDCS<0> nSDRAS nSDCAS MA<24:10> nWE MD<31:0> DQM<3:0> RDnWR Electrical, Mechanical, and Thermal Specification write(0) nop write(0) col col wd0_0 wd0_1 wd0_2 wd0_3 wd0_4 wd0_5 wd0_6 mask0 ...
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Intel® PXA270 Processor AC Timing Specifications Figure 6-10. SDRAM Fly-by DMA Timing SDCLK<1> SDCLK<2> SDCKE<1> read pre nop command nSDCS<0> nSDCS<2> nSDRAS nSDCAS col bank MA<24:10> nWE rd0 MD<31:0> 0b0000 DQM<3:0> RDnWR DVAL<0> DVAL<1> Latch data on rising edge of ...
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Table 6-16. ROM AC Specification (Sheet Symbols Parameters tromDOH MD hold from address valid Address valid to data valid for the tromAVDVF first read access Address valid to data valid for tromAVDVS subsequent reads of non-burst devices ...
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Intel® PXA270 Processor AC Timing Specifications Figure 6-11. 32-Bit Non-burst ROM, SRAM, or Flash Read Timing CLK_MEM nCS<0> MA<25:2> MA<1:0>(SA1110x='0') MA<1:0>(SA1110x='1') nADV(nSDCAS) nOE nWE RDnWR MD<31:0> DQM<3:0>(SA1110x='0') DQM<3:0>(SA1110x='1') nCSx or nSDCSx 6-20 tromAS tromAVDVS tromAVDVF 0b00 0b00 ...
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Figure 6-12. 32-Bit Burst-of-Eight ROM or Flash Read Timing CLK_MEM nCS<0> MA<25:5> MA<4:2> MA<1:0>(SA1110x='0') MA<1:0>(SA1110x='1') nADV(nSDCAS) nOE nWE RDnWR MD<31:0> DQM<3:0>(SA1110x='0') DQM<3:0>(SA1110x='1') nCSx or nSDCSx Electrical, Mechanical, and Thermal Specification tAS tromAVDVF tromAVDVS 0b00 0b00 ...
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Intel® PXA270 Processor AC Timing Specifications Figure 6-13. Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash Timing CLK_MEM nCS<0> MA<25:4> MA<3> MA<2:1> MA<0>(SA1110x='0') MA<0>(SA1110x='1') nADV(nSDCAS) nOE nWE RDnWR MD<15:0> DQM<1:0>(SA1110x='0') DQM<1:0>(SA1110x='1') nCSx or nSDCSx 6-22 tromAS address tromAVDVS tromAVDVF ...
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Figure 6-14. 16-bit ROM/Flash/SRAM Read for 4/2/1 Bytes Timing CLK_MEM nCS<0> tromAS addr MA<25:1> MA<0>(SA1110x='0') MA<0>(SA1110x='1') nADV(nSDCAS) tromCES nOE nWE RDnWR MD<15:0> 0b00 DQM<1:0>(SA1110x='0') mask DQM<1:0>(SA1110x='1') 32-bit read Applies to: 16-bit ROM or non-burst flash 16-bit SRAM NOTE: MSC0[RDF0] = ...
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Intel® PXA270 Processor AC Timing Specifications 6.4.4.1.2 Synchronous Flash Read Parameters and Timing Diagrams Table 6-17 lists the timing parameters used in Figure 6-16. Table 6-17. Synchronous Flash Read AC Specifications (Sheet Symbols Parameters MIN tffCLK SDCLK0 ...
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Table 6-17. Synchronous Flash Read AC Specifications (Sheet Symbols Parameters MIN MD<31:0> read data input setup tffSDIS TBD time from SDCLK<2:0> rise MD<31:0> read data input hold time tffSDIH TBD from SDCLK<2:0> rise NOTES: 1. SDCLK0 may ...
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Intel® PXA270 Processor AC Timing Specifications Figure 6-15. Synchronous Flash Burst-of-Eight Read Timing CLK_MEM SDCLK<0> MA<19:2> MA<1:0>(SA1110x=0) MA<1:0>(SA1110x=1) nCS<0> nADV(nSDCAS) nOE nWE MD<31:0> DQM<3:0>(SA1110x=0) DQM<3:0>(SA1110x=1) 6-26 0b00 0b00/0b01/0b10/0b11 CODE CODE+1 0b0000 corresponding mask value NOTES: 1) SXCNFG[CL] = 0b100 (CL ...
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Figure 6-16. Synchronous Flash Stacked Burst-of-Eight Read Timing CLK_MEM SDCLK<3> MA<19:2> MA<1:0>(SA1110x=0) MA<1:0>(SA1110x=1) nCS<0> nADV(nSDCAS) nOE nWE MD<31:0> DQM<3:0>(SA1110x=0) DQM<3:0>(SA1110x=1) Electrical, Mechanical, and Thermal Specification 0b00 0b00/0b01/0b10/0b11 CODE CODE+1 0b0000 corresponding mask value NOTE: SXCNFG[CL] = 0b100 ( ...
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Intel® PXA270 Processor AC Timing Specifications Figure 6-17 indicates which clock data would be latched following the assertion of nSDCAS(ADV), depending on the configuration of the SXCNFG[SXCLx] bit field. The period in the diagram indicated by different frequency configuration codes ...
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The burst read example shown in SXCNFG[SXCLx] is configured as 0b0100, representing a frequency configuration code equal to 3. The following example can be used to help determine the appropriate setting for SXCNFG[SXCLx]. Parameters defined by the processor: • tffSDOH ...
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Intel® PXA270 Processor AC Timing Specifications Figure 6-18. Synchronous Flash Burst Read Example SDCLK<0> tffSDOH nCS<0> nSDCAS (ADV#) tffSDOH MA MD 6.4.4.2 Flash Memory Write Parameters and Timing Diagrams Table 6-18 lists the AC specification for both burst and non-burst ...
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Table 6-18. Flash Memory AC Specification (Sheet Symbols Parameters tflashDOH MD hold from address valid nCS de-asserted after a read/write to tflashCD next nCS or nSDCS asserted (minimum) NOTES: 1. Numbers shown as integer multiples of the ...
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Intel® PXA270 Processor AC Timing Specifications Figure 6-20. 32-Bit Stacked Flash Write Timing CLK_MEM nWE tflashAS MA<25:2> MA<1:0> tflashASW nCS<0> or nCS<1> nOE RDnWR MD<31:0> DQM<3:0> nADV(nSDCAS) nCSx 6-32 tflashCD command address 0b00 tflashCEH tflashCES tflashAH tflashWL tflashDH tflashDSWH CMD ...
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Figure 6-21. 16-Bit Flash Write Timing CLK_MEM nCS<2> MA<25:1> MA<0> nWE nOE RDnWR MD<15:0> DQM<1:0> nADV(nSDCAS) nCSx or nSDCSx NOTE: MSC1[RDN2 MSC1[RDF2 MSC1[RRR2 6.4.5 SRAM Parameters and Timing Diagrams The following sections describe the ...
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Intel® PXA270 Processor AC Timing Specifications During writes, data pins are actively driven by the processor and are not three-stated, regardless of the states of the individual DQM signals. For SRAM writes, the DQM signals are used as byte enables. ...
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Figure 6-22. 32-Bit SRAM Write Timing CLK_MEM nCS<0> tsramAS MA<25:2> byte addr MA<1:0> tsramASW tsramCESW nWE nOE RDnWR MD<31:0> DQM<3:0> nCSx or nSDCSx nADV(nSDCAS) Electrical, Mechanical, and Thermal Specification byte addr byte addr tsramASW tsramAH tsramWL tsramWL ...
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Intel® PXA270 Processor AC Timing Specifications Figure 6-23. 16-bit SRAM Write for 4/2/1 Byte(s) Timing CLK_MEM nCS<2> tramAS addr MA<25:1> '0' MA<0> tsramCES tsramWL nWE nOE RDnWR tsramDSWH Bytes 1:0 MD<15:0> 0b00 DQM<1:0> nADV(nSDCAS) nCSx or nSDCSx 32-bit Write 6.4.6 ...
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Table 6-20. VLIO Timing Symbols Parameters tvlioAS Address setup to nCS asserted Address hold from nPWE/nOE de- tvlioAH asserted Address setup to nPWE/nOE tvlioASRW0 asserted (1st access) Address setup to nPWE/nOE tvlioASRWn asserted (next access(es)) tvlioCES nCS setup to nPWE/nOE ...
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Intel® PXA270 Processor AC Timing Specifications Figure 6-24. 32-Bit VLIO Read Timing CLK_MEM nCS<0> tvlioAS addr MA<25:2> MA<1:0>(SA1110x='0') MA<1:0>(SA1110x='1') tvlioASRW0 0 Waits nOE nPWE RDnWR RDY RDY_sync MD<31:0> DQM<3:0>(SA1110x='0') DQM<3:0>(SA1110x='1') nCSx or nSDCSx 6.4.6.2 Variable-Latency I/O Write Timing Figure 6-25 ...
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Figure 6-25. 32-Bit VLIO Write Timing CLK_MEM nCS<0> tvlioAS addr MA<25:2> MA<1:0> tvlioASRW0 tvlioCES 0 Waits nPWE nOE RDnWR RDY RDY_sync D0 MD<31:0> mask0 DQM<3:0> nCSx or nSDCSx NOTE: MSC0[RDF0 MSC0[RDN0 MSC0[RRR0 Electrical, Mechanical, ...
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Intel® PXA270 Processor AC Timing Specifications 6.4.7 Expansion-Card Interface Parameters and Timing Diagrams The following sections describe the read/write parameters and timing diagrams for CompactFlash* and PC Card* (expansion card) memory interfaces with the memory controller. Table 6-21 shows the ...
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Figure 6-26. Expansion-Card Memory or I/O 16-Bit Access Timing CLK_MEM nPCE[2],nPCE[1] MA[25:0],nPREG,PSKTSEL nPWE,nPOE,nPIOW,nPIOR nIOIS16 MD[15:0] (write) RDnWR nPWAIT MD[15:0] (read) Electrical, Mechanical, and Thermal Specification tcdCLPS tcdPHCH tcdAVCL tcdCMD tcdILCL tcdDVCL Intel® PXA270 Processor AC Timing Specifications Read Data Latch ...
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Intel® PXA270 Processor AC Timing Specifications Figure 6-27. Expansion-Card Memory or I/O 16-Bit Access to 8-Bit Device Timing CLK_MEM MA<25:1>,nPREG,PSKTSEL MA<0> nPCE<2> nPCE<1> nPIOW (or) nPIOR RDnWR nIOIS16 nPWAIT MD<7:0> (read) MD<7:0> (write) 6-42 Read Data Latch tcdAVCL tcdAVCL tcdCMD ...
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LCD Timing Specifications Figure 6-28 describes the LCD timing parameters. The LCD pin timing specifications are referenced to the pixel clock (L_PCLK_WR). Figure 6-28. LCD Timing Definitions L_PCLK_WR L_LDD[17:0] (rise) L_LDD[17:0] (fall) L_LCLK_A0 L_BIAS L_FCLK_RD Table 6-22. LCD Timing ...
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Intel® PXA270 Processor AC Timing Specifications 6.6 SSP Timing Specifications Figure 6-29 describes the SSP timing parameters. The SSP pin timing specifications are referenced to SSPCLK. Table 6-23 Note: In Figure 6-29, read the term “tSFMV” as “TSTXV.” Figure 6-29. ...
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Table 6-24. Timing Specification SSP Slave Mode Transmitting Data to External Peripheral Parameter tSFRM2TXD_output_delay tSCLK2TXD_output_delay Figure 6-31. Timing Diagram for SSP Slave Mode Receiving Data from External Peripheral PXA27 processor receiving data PXA27 processor receiving data PXA27x SSP (Slave Mode ...
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Intel® PXA270 Processor AC Timing Specifications Table 6-26. Boundary Scan Timing Specifications (Sheet Symbol TBSIS1 Input Setup to TCK TDI, TMS TBSIH1 Input Hold from TCK TDI, TMS TBSIS2 Input Setup to TCK nTRST TBSIH2 Input Hold ...
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Glossary 3G: An industry term used to describe the next, still-to-come generation of wireless applications. It represents a move from circuit-switched communications (where a device user has to dial network) to broadband, high-speed, packet-based wireless networks (which ...
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Intel® PXA270 Processor Glossary BGA: Ball Grid Array BFSK: binary frequency shift keying. A coding scheme for digital data. Bit: A unit of information used by digital computers. Represents the smallest piece of addressable memory within a computer. A bit ...
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Several versions of the standard are still under development. CDMA should increase network capacity for wireless carriers and improve the quality of wireless messaging. CDMA is an alternative to GSM. CDPD: ...
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Intel® PXA270 Processor Glossary Default Pipe: The message pipe created by the USB System Software to pass control and status information between the host and a USB device’s endpoint zero. Device: A logical or physical entity that performs a function. ...
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End User: The user of a host. Endpoint: See device endpoint. Endpoint Address: The combination of an endpoint number and an endpoint direction on a USB device. Each endpoint address supports data transfer in one direction. Endpoint Direction: The direction ...
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Intel® PXA270 Processor Glossary Full-duplex: Computer data transmission occurring in both directions simultaneously. Full-speed: USB operation at 12 Mb/s. See also low-speed and high-speed. Function: A USB device that provides a capability to the host, such as an ISDN connection, ...
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IMMU: Instruction Memory Management Unit, part of the Intel XScale® core. I-Mode: A Japanese wireless service for transferring packet-based data to handheld devices created by NTT DoCoMo. I-Mode is based on a compact version of HTML and does not currently ...
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Intel® PXA270 Processor Glossary kB/s: Transmission rate expressed in kilobytes per second. Little endian: Method of storing data that places the least significant byte of multiple-byte values at lower storage addresses. For example, a 16-bit integer stored in little endian ...
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OFDM: See Orthogonal Frequency Division Multiplexing. Orthogonal Frequency Division Multiplexing: A special form of multi-carrier modulation multi-path channel, most conventional modulation techniques are sensitive to inter-symbol interference unless the channel symbol rate is small compared to the delay ...
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Intel® PXA270 Processor Glossary Port: Point of access to or from a system or circuit. For the USB, the point where a USB device is attached. Power On Reset (POR): Restoring a storage device, register, or memory to a predetermined ...
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Sample: The smallest unit of data on which an endpoint operates; a property of an endpoint. Sample Rate (Fs): The number of samples per second, expressed in Hertz (Hz). Sample Rate Conversion (SRC): A dedicated implementation of the RA process ...
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Intel® PXA270 Processor Glossary SSE2: Streaming SIMD Extensions 2: for Intel Architecture machines, 144 new instructions, a 128-bit SIMD integer arithmetic and 128-bit SIMD double precision floating point instructions, enabling enhanced multimedia experiences. SSP: Synchronous Serial Port SSTL: Stub series ...
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Time-out: The detection of a lack of bus activity for some predetermined interval. Token Packet: A type of packet that identifies what transaction performed on the bus. TPV: Third Party Vendor Transaction: The delivery of service to ...
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Intel® PXA270 Processor Glossary W-CDMA: Wideband CDMA, a third generation wireless technology under development that allows for high-speed, high-quality data transmission. Derived from CDMA, W-CDMA digitizes and transmits wireless data over a broad range of frequencies. It requires more bandwidth ...
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Index A About This Document ........................................................1 AC Timing Specifications ..................................................1 AC Test Load Specifications ......................................1 GPIO Timing Specifications ....................................11 JTAG Boundary Scan Timing Specifications ..........45 LCD Timing Specifications .....................................43 Memory and Expansion-Card Timing Specifications 12 Flash Memory Parameters and Timing ...
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Index Index-2 Intel® PXA270 Processor EMTS ...