MC68HC68 MOTOROLA [Motorola, Inc], MC68HC68 Datasheet - Page 13

• Manufacturer Part Number: MC68HC68
• Description: Real-Time Clock plus RAM with Serial Interface
• Manufacturer: MOTOROLA [Motorola, Inc]

CLKOUT
Clock Output (Pin 1)
one of the seven selectable frequencies (or this output can
be reset low). The contents of the three least significant bit
positions in the clock control register determine the output
frequency (50% duty cycle, except 2 Hz in the 50 Hz time–
base mode). During power–down operation (Power–Down
bit in the interrupt control register set high), the CLKOUT pin
is reset low.
CPUR
CPU Reset (Pin 2)
requires an external pullup resistor. This active low output
can be used to drive the reset pin of a microprocessor to per-
mit orderly power–up/power–down. The CPUR output is low
from 15 to 40 ms when the watchdog function detects a CPU
failure (see Table 2). The low level time is determined by the
input frequency source selected as the time standard. CPUR
is reset low when power–down is initiated.
INT
Interrupt (Pin 3)
transistor and must be tied to an external pullup resistor.
Interrupt is activated to a low level when any one of the fol-
lowing takes place:
put after the selected periodic interval occurs. This is also
true when conditions 1 and 2 activate the interrupt. If power–
down has been previously selected, the interrupt also sets
the power–up function only if power is supplied to the V SYS
pin to the proper threshold level above V BATT .
SCK
Serial Clock (Pin 4)
the on–chip interface logic. SCK retains its previous state if
the line driving it goes into a high–impedance state. In other
words, if the source driving SCK goes to the high–impedance
state, the previous low or high level is retained by on–chip
control circuitry.
MOSI
Master Out Slave In (Pin 5)
face logic by SCK if the logic is enabled. Data is shifted in,
MOTOROLA
This signal is the buffered clock output which can provide
This pin provides an N channel, open–drain output and
This active–low output is driven from a single N channel
The status register must be read to reset the interrupt out-
This serial clock input is used to shift data into and out of
The serial data present at this port is latched into the inter-
1. Power sense operation is selected (Power Sense Bit in
2. A previously set alarm time occurs. The alarm bit in the
3. A previously selected periodic interrupt signal activates.
the interrupt control register is set high) and a power
failure occurs.
status register and the interrupt signal are delayed
30.5 ms when 32 kHz or 1 MHz operation is selected,
15.3 ms for 2 MHz operation, and 7.6 ms for 4 MHz
operation.
PIN DESCRIPTIONS
either on the rising or falling edges of SCK, with the most sig-
nificant bit (MSB) first.
CPOL bit determines which is the active edge of SCK. If SCK
is high when SS goes high, the state of the CPOL bit is high.
Likewise, if a rising edge of SS occurs while SCK is low (see
Figure 13), then the CPOL bit in the microcomputer is low.
into high–impedance state. In other words, if the source
driving MOSI goes to the high–impedance state, the pre-
vious low or high level is retained by on–chip control circuitry.
MISO
Master In Slave Out (Pin 6)
interface logic by SCK if the logic is enabled. Data is shifted
out, either on the rising or falling edge of SCK, with the most
significant bit (MSB) first. The state of the CPOL bit in the
microcomputer determines which is the active edge of SCK
(see Figure 13).
SS
Slave Select (Pin 7)
logic; otherwise the logic is in a reset state and the MISO pin
is in the high–impedance state. The watchdog circuit is
toggled at this pin. SS has an internal pulldown device.
Therefore, if SS is in a low state before going to high imped-
ance, SS can be left in a high–impedance state. That is, if the
source driving SS goes to the high–impedance state, the
previous low level is retained by on–chip control circuitry.
V SS
Ground (Pin 8)
PSE
Power Supply Enable (Pin 9)
power and is enabled high under any one of the following
conditions:
of the interrupt control register.
POR
Power–On Reset (Pin 10)
nal power–on reset signal using an external RC network (see
Figures 18 through 21). Both control registers and frequency
dividers for the oscillator and line inputs are reset. The status
register is reset except for the first time–up bit (bit 4), which is
set high. At the end of the power–on reset, single–supply or
battery–backup mode is selected at this time, determined by
the state of V SYS .
In Motorola’s microcomputers with SPI, the state of the
MOSI retains its previous state if the line driving it goes
The serial data present at this port is shifted out of the
When high, the slave select input activates the interface
This pin is connected to ground.
The power supply enable output is used to control system
PSE is reset low by writing a high into the power–down bit
This active–low Schmitt–trigger input generates an inter-
This pin may be more aptly named first–time–up reset.
1. V SYS rises above the V BATT voltage after V SYS is
2. An interrupt occurs (if the V SYS pin is powered up 0.7 V
3. A power–on reset occurs (if the V SYS pin is powered up
reset low by a system failure.
above V BATT ).
0.7 V above V BATT ).
MC68HC68T1
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