MC68HC68 MOTOROLA [Motorola, Inc], MC68HC68 Datasheet - Page 6

• Manufacturer Part Number: MC68HC68
• Description: Real-Time Clock plus RAM with Serial Interface
• Manufacturer: MOTOROLA [Motorola, Inc]

32 x 8 RAM (see Figure 5). Communication with the device
may be established via a serial peripheral interface (SPI) or
MICROWIRE bus. In addition to the clock/calendar data from
seconds to years, and systems flexibility provided by the
32–byte RAM, the clock features computer handshaking with
an interrupt output and a separate square–wave clock output
that can be one of seven different frequencies. An alarm cir-
cuit is available that compares the alarm latches with the se-
conds, minutes, and hours time counters and activates the
interrupt output when they are equal. The clock is specifically
designed to aid in power–up/power–down applications and
offers several pins to aid the designer of battery–backup sys-
tems.
CLOCK/CALENDAR
string of counters that is toggled by a 1 Hz input. The 1 Hz
input is derived from the on–chip oscillator that utilizes one of
four possible external crystals or that can be driven by an ex-
ternal frequency source. The 1 Hz trigger to the counters can
also be supplied by a 50 or 60 Hz source that is connected to
the LINE input pin.
in 12– or 24–hour format. An AM/PM indicator is available
that once set, toggles at 12:00 AM and 12:00 PM. The calen-
dar counters consist of day of week, date of month, month,
and year information. Data in the counters is in BCD format.
The hours counter utilizes BCD for hours data plus bits for
12/24 hour and AM/PM modes. The seven time counters are
read serially at addresses $20 through $26. The time count-
ers are written to at addresses $A0 through $A6. (See Fig-
ures 5 and 6 and Table 1.)
32 x 8 GENERAL–PURPOSE RAM
RAM is read at addresses $00 through $1F and written to at
addresses $80 through $9F (see Figure 5).
ALARM
loading the desired data. (See Serial Peripheral Interface.)
The alarm latches consist of seconds, minutes, and hours
registers. When their outputs equal the values of the se-
conds, minutes, and hours time counters, an interrupt is gen-
erated. The interrupt output goes low if the alarm bit in the
status register is set and the interrupt output is activated after
an alarm time is sensed (see Pin Descriptions, INT Pin). To
preclude a false interrupt when loading the time counters, the
alarm interrupt bit in the interrupt control register should be
reset. This procedure is not required when the alarm time is
being loaded.
WATCHDOG FUNCTION
set high, the clock’s slave select pin must be toggled at regu-
lar intervals without a serial data transfer. If SS is not toggled
at the rate shown in Table 2, the MC68HC68T1 supplies a
MC68HC68T1
6
The real–time clock consists of a clock/calendar and a
The clock/calendar portion of this device consists of a long
The time counters offer seconds, minutes, and hours data
The real–time clock also has a static 32 x 8 RAM. The
The alarm is set by accessing the three alarm latches and
When Watchdog (bit 7) in the interrupt control register is
OPERATING CHARACTERISTICS
CPU reset pulse at Pin 2 and Watchdog (bit 6) in the status
register is set (see Figure 7). Typical service and reset times
are shown in Table 2.
CLOCK OUT
control register selects one of seven possible output fre-
quencies. (See Clock Control Register.) This square–wave
signal is available at the CLKOUT pin. When the power–
down operation is initialized, the output is reset low.
CONTROL REGISTER AND STATUS REGISTER
clock control and interrupt control registers, which are read/
write registers. Another register, the status register, is avail-
able to indicate the operating conditions. The status register
is a read–only register, and a read operation resets status
bits.
MODE SELECT
end of power–on reset selects the device to be in the single–
supply mode or battery–backup mode.
Single–Supply Mode
CLKOUT, PSE, and CPUR are enabled high and the device
is completely operational. CPUR is asserted low if the volt-
age level at the V SYS pin subsequently falls below V BATT +
0.7 V. If CLKOUT, PSE, and CPUR are reset low due to a
power–down instruction, V SYS brought low and then pow-
ered high re–enables these outputs.
supply is available and V DD , V BATT , and V SYS are tied to-
gether to the supply.
Battery–Backup Mode
er–on reset, CLKOUT, PSE, CPUR, and SS are disabled
(CLKOUT, PSE, and CPUR low). This condition is held until
V SYS rises to a threshold (approximately 0.7 V) above V BATT .
CLKOUT, PSE, and CPUR are then enabled and the device
is operational. If V SYS falls below a threshold above V BATT ,
the outputs CLKOUT, PSE, and CPUR are reset low.
tied to the 5 V supply and is not receiving voltage from a sup-
ply. A rechargeable battery is connected to the V BATT pin,
causing a POR while V SYS = 0 V. The device retains data
and keeps time down to a minimum V BATT voltage of 2.2 V.
it until main power is cycled once.
POWER CONTROL
sense and power–down/power–up. Two pins are involved in
power sensing, the LINE input pin and the INT output pin.
Two additional pins, PSE and V SYS , are utilized during
power–down/power–up operation.
The value in the three least significant bits of the clock
The operation of the real–time clock is controlled by the
The voltage level that is present at the V SYS input pin at the
If V SYS is powered up when power–on reset is completed;
An example of the single–supply mode is where only one
If V SYS is not powered up (V SYS = 0 V) at the end of pow-
An example of battery–backup operation occurs if V SYS is
The power consumption may not settle to the specified lim-
Power control is composed of two operations, power–
MOTOROLA