MC68HC705C9ACB MOTOROLA [Motorola, Inc], MC68HC705C9ACB Datasheet
MC68HC705C9ACB
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MC68HC705C9ACB Summary of contents
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Freescale Semiconductor, Inc. M68HC05 Microcontrollers WWW.MOTOROLA.COM/SEMICONDUCTORS For More Information On This Product, Go to: www.freescale.com MC68HC705C9A Advance Information MC68HC705C9A/D Rev. 4, 2/2002 ...
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Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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Freescale Semiconductor, Inc. MC68HC705C9A Advance Information To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the ...
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Freescale Semiconductor, Inc. Revision History Revision Date Level October, 2001 3.0 February, 2002 4.0 Advance Information 4 Revision History Description Format update to current publication standards Figure 12-10. SPI Slave Timing Diagram labels for MISO and MOSI and subtitle for ...
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Freescale Semiconductor, Inc. Advance Information — MC68HC705C9A Section 1. General Description . . . . . . . . . . . . . . . . . . . . 21 Section 2. Memory . . . . . ...
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Freescale Semiconductor, Inc. List of Sections Advance Information 6 For More Information On This Product, List of Sections Go to: www.freescale.com MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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Freescale Semiconductor, Inc. Advance Information — MC68HC705C9A 1.1 1.2 1.3 1.4 1.5 1.5.1 1.5.2 1.6 1.7 1.7.1 1.7.2 1.7.3 1.7.4 1.7.5 1.7.6 1.7.7 1.7.8 1.7.9 1.7.10 1.7.11 MC68HC705C9A — Rev. 4.0 MOTOROLA For More Information On This Product, Section 1. ...
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Freescale Semiconductor, Inc. Table of Contents 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Advance Information 8 For More Information On This Product, Section 2. Memory ...
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Freescale Semiconductor, Inc. 5.1 5.2 5.3 5.4 5.5 5.6 5.6.1 5.6.2 5.7 5.8 5.9 5.10 5.10.1 5.10.2 6.1 6.2 6.3 6.4 7.1 7.2 7.3 7.4 MC68HC705C9A — Rev. 4.0 MOTOROLA For More Information On This Product, Section 5. Resets Contents ...
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Freescale Semiconductor, Inc. Table of Contents 7.5 7.6 8.1 8.2 8.3 8.3.1 8.3.2 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.5 8.6 Section 9. Serial Communications Interface (SCI) 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 Advance Information 10 ...
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Freescale Semiconductor, Inc. 9.10 9.11 9.12 9.13 9.14 9.14.1 9.14.2 9.14.3 9.14.4 9.14.5 10.1 10.2 10.3 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.5 10.6 10.6.1 10.6.2 10.6.3 11.1 11.2 MC68HC705C9A — Rev. 4.0 MOTOROLA For More Information On This Product, Address ...
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Freescale Semiconductor, Inc. Table of Contents 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.3.7 11.3.8 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.5 11.6 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 5.0-Vdc Serial Peripheral Interface Timing . . ...
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Freescale Semiconductor, Inc. 13.1 13.2 13.3 13.4 13.5 13.6 14.1 14.2 14.3 A.1 A.2 A.3 A.4 A.5 MC68HC705C9A — Rev. 4.0 MOTOROLA For More Information On This Product, Section 13. Mechanical Specifications Contents . . . . . . . ...
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Freescale Semiconductor, Inc. Table of Contents Advance Information 14 For More Information On This Product, Table of Contents Go to: www.freescale.com MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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Freescale Semiconductor, Inc. Advance Information — MC68HC705C9A Figure 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 2-1 2-2 2-3 2-4 3-1 3-2 4-1 5-1 5-2 5-3 5-4 5-5 5-6 6-1 MC68HC705C9A — Rev. 4.0 MOTOROLA For More Information On This ...
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Freescale Semiconductor, Inc. List of Figures Figure 7-1 7-2 8-1 8-2 8-3 8-4 8-5 8-6 8-7 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 SCI Control Register 2 (SCCR2 ...
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Freescale Semiconductor, Inc. Figure 12-4 TCAP Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . 139 12-5 External Interrupt Timing . ...
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Freescale Semiconductor, Inc. List of Figures Advance Information 18 For More Information On This Product, List of Figures Go to: www.freescale.com MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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Freescale Semiconductor, Inc. Advance Information — MC68HC705C9A Table 4-1 5-1 9-1 9-2 10-1 SPI Clock Rate Selection . . . . . . . . . . . . . . . . . . . . . . . ...
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Freescale Semiconductor, Inc. List of Tables Advance Information 20 For More Information On This Product, List of Tables Go to: www.freescale.com MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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Freescale Semiconductor, Inc. Advance Information — MC68HC705C9A 1.1 Contents 1.2 1.3 1.4 1.5 1.5.1 1.5.2 1.6 1.7 1.7.1 1.7.2 1.7.3 1.7.4 1.7.5 1.7.6 1.7.7 1.7.8 1.7.9 1.7.10 1.7.11 1.2 Introduction The MC68HC705C9A HCMOS microcomputer is a member of the M68HC05 ...
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Freescale Semiconductor, Inc. General Description the MC68HC05C12A. The MC68HC705C9A memory map consists of 12,092 bytes of user EPROM and 176 bytes of RAM when it is configured as an MC68HC05C12A and 15,932 bytes of user EPROM and 352 bytes of ...
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Freescale Semiconductor, Inc. BOOT ROM — 239 BYTES USER EPROM — 15,936 BYTES USER RAM —352 BYTES CPU CONTROL IRQ M68HC05 MCU RESET RESET STACK POINTER PROGRAM COUNTER OSC1 INTERNAL OSCILLATOR OSC2 ...
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Freescale Semiconductor, Inc. General Description 1.4 Configuration Options The options and functions of the MC68HC705C9A can be configured to emulate either the MC68HC05C9A or the MC68HC05C12A. The ROM device MC68HC05C9A has eight ROM mask options to select external interrupt/internal pullup ...
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Freescale Semiconductor, Inc. • • • When configured as an MC68HC05C12A: • • • • • • • • • MC68HC705C9A — Rev. 4.0 MOTOROLA For More Information On This Product, SPI output signals (MOSI, MISO, and SCK) require the ...
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Freescale Semiconductor, Inc. General Description 1.5 Mask Options The following two mask option registers are used to select features controlled by mask changes on the MC68HC05C9A and the MC68HC05C12A: • • The mask option registers are EPROM locations which must ...
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Freescale Semiconductor, Inc. 1.5.2 C12 Mask Option Register (C12MOR) The C12MOR register, shown in options: • • • • $3FF1 Read: Write: C12A — C12A/C9A Mode Select Bit This read/write bit selects between C12A configuration and C9A configuration. C12IRQ — ...
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Freescale Semiconductor, Inc. General Description STOPDIS — STOP Instruction Disable Bit This read-only bit allows emulation of the “STOP disable” mask option on the MC68HC05C12A. (See configured in MC68HC05C9A mode, this bit has no effect and will be forced to ...
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Freescale Semiconductor, Inc. 1.6 Software-Programmable Options (MC68HC05C9A Mode Only) The C9A option register (OR), shown in configured in C9A mode. This register contains the programmable bits for the following options: • • This register must be written to by user ...
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Freescale Semiconductor, Inc. General Description 1.7 Functional Pin Descriptions Figure assignments for the available packages. A functional description of the pins follows. NOTE: A line over a signal name indicates an active low signal. For example, RESET is active high ...
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Freescale Semiconductor, Inc. MC68HC705C9A — Rev. 4.0 MOTOROLA For More Information On This Product, 42 RESET 1 41 IRQ PA7 39 4 PA6 38 5 PA5 PA4 7 35 PA3 8 34 ...
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Freescale Semiconductor, Inc. General Description NOTE: The above 44-pin PLCC pin assignment diagram is for compatibility with MC68HC05C9A. To allow compatibility with the 44-pin PLCC MC68HC05C12A, pin17 and pin18 must be tied together and pin 39 and pin 40 also ...
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Freescale Semiconductor, Inc. 1.7.1 V and Power is supplied to the MCU using these two pins. V supply and V 1.7 This pin provides the programming voltage to the EPROM array. For normal operation, V ...
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Freescale Semiconductor, Inc. General Description 1.7.3 IRQ This interrupt pin has an option that provides two different choices of interrupt triggering sensitivity. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. Refer ...
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Freescale Semiconductor, Inc. 1.7.8 PA0–PA7 These eight I/O lines comprise port A. The state of each pin is software programmable and all port A pins are configured as inputs during reset. Refer to 1.7.9 PB0–PB7 These eight I/O lines comprise ...
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Freescale Semiconductor, Inc. General Description Advance Information 36 For More Information On This Product, General Description Go to: www.freescale.com MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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Freescale Semiconductor, Inc. Advance Information — MC68HC705C9A 2.1 Contents 2.2 2.3 2.4 2.5 2.6 2.7 2.2 Introduction The MCU has a 16-Kbyte memory map when configured as either an MC68HC05C9A or an MC68HC05C12A. The memory map consists of registers (I/O, ...
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Freescale Semiconductor, Inc. Memory 2.3 RAM The main user RAM consists of 176 bytes at $0050–$00FF. This RAM area is always present in the memory map and includes a 64-byte stack area. The stack pointer can access 64 bytes of ...
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Freescale Semiconductor, Inc. $0000 I/O REGISTERS 32 BYTES $001F $0020 USER EPROM RAM 48 BYTES 48 BYTES RAM0 = 0 RAM0 = 1 $004F $0050 RAM 176 BYTES $00BF $00C0 (STACK) 64 BYTES $00FF $0100 USER EPROM RAM 128 BYTES ...
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Freescale Semiconductor, Inc. Memory $0000 I/O REGISTERS 32 BYTES $001F $0020 USER EPROM 48 BYTES $004F $0050 RAM 176 BYTES $00BF $00C0 (STACK) 64 BYTES $00FF $0100 UNUSED 3840 BYTES $0FFF $1000 USER EPROM 12,032 BYTES $3EFF $3F00 BOOTLOADER ROM ...
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Freescale Semiconductor, Inc. 2.5 EPROM Security A security feature has been incorporated into the MC68HC705C9A to help prevent external access to the contents of the EPROM in any mode of operation. Once enabled, this feature can be disabled only by ...
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Freescale Semiconductor, Inc. Memory Advance Information 42 For More Information On This Product, Addr Register Name $0000 Port A Data Register $0001 Port B Data Register $0002 Port C Data Register $0003 Port D Data Register $0004 Port A Data ...
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Freescale Semiconductor, Inc. Addr. Register Name Read: Port A Data Register $0000 (PORTA) See page 69. Reset: Read: Port B Data Register $0001 (PORTB) See page 70. Reset: Read: Port C Data Register $0002 (PORTC) See page 71. Reset: Read: ...
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Freescale Semiconductor, Inc. Memory Addr. Register Name $0009 Unimplemented SPI Control Register $000A (SPCR) See page 109. Reset: SPI Status Register $000B (SPSR) See page 111. Reset: SPI Data Register $000C (SPDR) See page 113. Reset: SCI Baud Rate Register ...
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Freescale Semiconductor, Inc. Addr. Register Name Read: Timer Control Register $0012 (TCR) See page 76. Reset: Read: Timer Status Register $0013 (TSR) See page 78. Reset: Read: Bit 15 Input Capture Register High $0014 (ICRH) See page 81. Reset: Read: ...
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Freescale Semiconductor, Inc. Memory Addr. Register Name Alternate Timer Register Low $001B (ATRL) See page 80. Reset: EPROM Programming $001C Register (EPR) Reset: COP Reset Register $001D (COPRST) C9A Only See page 61. Reset: COP Control Register $001E (COPCR) C9A ...
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Freescale Semiconductor, Inc. Advance Information — MC68HC705C9A 3.1 Contents 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.2 Introduction This section contains the basic programmers model and the registers contained in the CPU. 3.3 CPU Registers The MCU contains five registers ...
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Freescale Semiconductor, Inc. Central Processor Unit (CPU 3.3.1 Accumulator (A) The accumulator is a general-purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 3.3.2 Index Register (X) The index register is ...
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Freescale Semiconductor, Inc. 3.3.3 Program Counter (PC) The program counter is a 16-bit register that contains the address of the next byte to be fetched. 3.3.4 Stack Pointer (SP) The stack pointer contains the address of the next free location ...
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Freescale Semiconductor, Inc. Central Processor Unit (CPU) Negative (N) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Zero (Z) When set, this bit indicates that the result of the last ...
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Freescale Semiconductor, Inc. Advance Information — MC68HC705C9A 4.1 Contents 4.2 4.3 4.4 4.5 4.6 4.7 4.2 Introduction The MCU can be interrupted by five different sources, four maskable hardware interrupts, and one non-maskable software interrupt: • • • • • ...
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Freescale Semiconductor, Inc. Interrupts NOTE: The current instruction is the one already fetched and being operated on. When the current instruction is complete, the processor checks all pending hardware interrupts. If interrupts are not masked (CCR I bit clear) and ...
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Freescale Semiconductor, Inc. 4.3 Non-Maskable Software Interrupt (SWI) The SWI is an executable instruction and a non-maskable interrupt executed regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts enabled), ...
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Freescale Semiconductor, Inc. Interrupts 4.5 Timer Interrupt Three different timer interrupt flags cause a timer interrupt whenever they are set and enabled. The interrupt flags are in the timer status register (TSR), and the enable bits are in the timer ...
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Freescale Semiconductor, Inc RESTORE REGISTERS FROM STACK: CCR,A,X,PC MC68HC705C9A — Rev. 4.0 MOTOROLA For More Information On This Product, FROM RESET I BIT IN CCR SET? N CLEAR IRQ IRQ OR PORT B Y REQUEST EXTERNAL LATCH INTERRUPT ...
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Freescale Semiconductor, Inc. Interrupts Advance Information 56 For More Information On This Product, Interrupts Go to: www.freescale.com MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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Freescale Semiconductor, Inc. Advance Information — MC68HC705C9A 5.1 Contents 5.2 5.3 5.4 5.5 5.6 5.6.1 5.6.2 5.7 5.8 5.9 5.10 5.10.1 5.10.2 MC68HC705C9A — Rev. 4.0 MOTOROLA For More Information On This Product, Introduction . . . . . . ...
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Freescale Semiconductor, Inc. Resets 5.2 Introduction The MCU can be reset four ways: by the initial power-on reset function active low input to the RESET pin, by the COP the clock monitor. A reset immediately stops ...
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Freescale Semiconductor, Inc. 5.4 RESET Pin The function of the RESET pin is dependent on whether the device is configured as an MC68HC05C9A or an MC68HC05C12A. When the MC68HC05C12A configuration, the pin is input only. When in ...
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Freescale Semiconductor, Inc. Resets 5.5 Computer Operating Properly (COP) Reset This device includes a watchdog COP feature which guards against program run-away failures. A timeout of the computer operating properly (COP) timer generates a COP reset. The COP watchdog is ...
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Freescale Semiconductor, Inc. 5.6.1 C9A COP Reset Register This write-only register, shown in $001D Read: Write: Reset: The sequence required to reset the COP timer is: • • Both write operations must occur in the order listed, but any number ...
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Freescale Semiconductor, Inc. Resets 5.6.2 C9A COP Control Register The COP control register, shown in functions: • • • and flags the following conditions: • • $001E Read: Write: Reset: COPF — Computer Operating Properly Flag Reading the COP control ...
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Freescale Semiconductor, Inc. CM1 — COP Mode Bit 1 Used in conjunction with CM0 to establish the COP timeout period, this bit is readable any time. COPE, CM1, and CM0 together may be written with a single write, only once, ...
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Freescale Semiconductor, Inc. Resets 5.8 MC68HC05C12A Compatible COP Clear Register The COP clear register, shown in counter. $3FF0 Read: Write: Reset: COPC — Computer Operating Properly Clear Bit Preventing a COP reset is achieved by writing the ...
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Freescale Semiconductor, Inc. In the event that an inadvertent STOP instruction is executed, neither COP will allow the system to recover. The MC68HC705C9A offers two solutions to this problem, one available in C9A mode (see Monitor Instruction Disable 5.10.1 Clock ...
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Freescale Semiconductor, Inc. Resets Advance Information 66 For More Information On This Product, Resets Go to: www.freescale.com MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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Freescale Semiconductor, Inc. Advance Information — MC68HC705C9A 6.1 Contents 6.2 6.3 6.4 6.2 Introduction This section describes the low-power modes. 6.3 Stop Mode The STOP instruction places the MCU in its lowest-power consumption mode. In stop mode, the internal oscillator ...
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Freescale Semiconductor, Inc. Low-Power Modes (1) OSC1 RESET (2) IRQ (3) IRQ INTERNAL CLOCK INTERNAL ADDRESS BUS Notes: 1. Represents the internal gating of the OSC1 pin 2. IRQ pin edge-sensitive mask option 3. IRQ pin level and edge-sensitive mask ...
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Freescale Semiconductor, Inc. Advance Information — MC68HC705C9A 7.1 Contents 7.2 7.3 7.4 7.5 7.6 7.2 Introduction This section briefly describes the 31 input/output (I/O) lines arranged as one 7-bit and three 8-bit ports. All of these port pins are programmable ...
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Freescale Semiconductor, Inc. Input/Output (I/O) Ports INTERNAL HC05 CONNECTIONS 7.4 Port B Port 8-bit bidirectional port. The port B data register is at $0001 and the data direction register (DDR $0005. The contents of the ...
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Freescale Semiconductor, Inc. 7.5 Port C Port 8-bit bidirectional port. The port C data register is at $0002 and the data direction register (DDR $0006. The contents of the port C data register are indeterminate ...
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Freescale Semiconductor, Inc. Input/Output (I/O) Ports PORT B EXTERNAL INTERRUPT MASK OPTION REGISTER CONTROLLED READ $0005 WRITE $0005 RESET WRITE $0001 READ $0001 SOFTWARE OR MASK OPTION REGISTER CONTROLLED DEPENDENT ON CONFIGURATION FROM OTHER PORT B PINS IRQ RESET EXTERNAL ...
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Freescale Semiconductor, Inc. Advance Information — MC68HC705C9A 8.1 Content 8.2 8.3 8.3.1 8.3.2 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.5 8.6 8.2 Introduction This section describes the operation of the 16-bit capture/compare timer. Figure 8-1 MC68HC705C9A — Rev. 4.0 ...
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Freescale Semiconductor, Inc. Capture/Compare Timer TIMER STATUS 8.3 Timer Operation The core of the capture/compare timer is a 16-bit free-running counter. The counter provides the timing reference for the input capture and output compare functions. The input capture and output ...
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Freescale Semiconductor, Inc. Because the counter is 16 bits long and preceded by a fixed divide-by-4 prescaler, the counter rolls over every 262,144 internal clock cycles. Timer resolution with a 4-MHz crystal 8.3.1 Input Capture The input ...
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Freescale Semiconductor, Inc. Capture/Compare Timer 8.4 Timer I/O Registers The following I/O registers control and monitor timer operation: • • • • • • 8.4.1 Timer Control Register The timer control register (TCR), shown in functions: • • • • ...
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Freescale Semiconductor, Inc. ICIE — Input Capture Interrupt Enable Bit This read/write bit enables interrupts caused by an active signal on the TCAP pin. Resets clear the ICIE bit. OCIE — Output Compare Interrupt Enable Bit This read/write bit enables ...
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Freescale Semiconductor, Inc. Capture/Compare Timer 8.4.2 Timer Status Register The timer status register (TSR), shown in signal the following conditions: • • • $0013 Read: Write: Reset: ICF — Input Capture Flag The ICF bit is set automatically when an ...
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Freescale Semiconductor, Inc. 8.4.3 Timer Registers The timer registers (TRH and TRL), shown in current high and low bytes of the 16-bit counter. Reading TRH before reading TRL causes TRL to be latched until TRL is read. Reading TRL after ...
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Freescale Semiconductor, Inc. Capture/Compare Timer 8.4.4 Alternate Timer Registers The alternate timer registers (ATRH and ATRL), shown in contain the current high and low bytes of the 16-bit counter. Reading ATRH before reading ATRL causes ATRL to be latched until ...
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Freescale Semiconductor, Inc. 8.4.5 Input Capture Registers When a selected edge occurs on the TCAP pin, the current high and low bytes of the 16-bit counter are latched into the input capture registers (ICRH and ICRL). Reading ICRH before reading ...
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Freescale Semiconductor, Inc. Capture/Compare Timer 8.4.6 Output Compare Registers When the value of the 16-bit counter matches the value in the output compare registers (OCRH and OCRL), the planned TCMP pin action takes place. Writing to OCRH before writing to ...
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Freescale Semiconductor, Inc. 8.5 Timer During Wait Mode The CPU clock halts during the wait mode, but the timer remains active. If interrupts are enabled, a timer interrupt will cause the processor to exit the wait mode. 8.6 Timer During ...
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Freescale Semiconductor, Inc. Capture/Compare Timer Advance Information 84 For More Information On This Product, Capture/Compare Timer Go to: www.freescale.com MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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Freescale Semiconductor, Inc. Advance Information — MC68HC705C9A Section 9. Serial Communications Interface (SCI) 9.1 Content 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13 9.14 9.14.1 9.14.2 9.14.3 9.14.4 9.14.5 MC68HC705C9A — Rev. 4.0 MOTOROLA For More ...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 9.2 Introduction This section describes the on-chip asynchronous serial communications interface (SCI). The SCI allows full-duplex, asynchronous, RS232 or RS422 serial communication between the MCU and remote devices, including other MCUs. The transmitter ...
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Freescale Semiconductor, Inc. INTERNAL BUS TRANSMIT $0011 DATA REGISTER TRANSMIT TDO DATA SHIFT PIN REGISTER 7 TRDE TE TRANSMITTER CONTROL 7 R8 Figure 9-1. Serial Communications Interface Block Diagram NOTE: The serial communications data register (SCI SCDR) is controlled by ...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 9.4 SCI Receiver Features Features of the SCI receiver include: • • • • • • 9.5 SCI Transmitter Features Features of the SCI transmitter include: • • • 9.6 Functional Description A ...
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Freescale Semiconductor, Inc. register is synchronized with the bit rate clock (see is transmitted least significant bit first. Upon completion of data transmission, the transmission complete flag (TC) in the SCSR is set (provided no pending data, preamble, or break ...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 9.7 Data Format Receive data or transmit data is the serial data that is transferred to the internal data bus from the receive data input pin (RDI) or from the internal bus to ...
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Freescale Semiconductor, Inc. The receiver is placed in wakeup mode by setting the receiver wakeup bit (RWU) in the SCCR2 register. While RWU is set, all of the receiver- related status flags (RDRF, IDLE, OR, NF, and FE) are inhibited ...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 9.11 Receive Data In (RDI) Receive data is the serial data that is applied through the input line and the SCI to the internal bus. The receiver circuitry clocks the input at a ...
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Freescale Semiconductor, Inc. 9.12 Start Bit Detection When the input (idle) line is detected low tested for three more sample times (referred to as the start edge verification samples in Figure logic 0, a valid start bit has ...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 9.13 Transmit Data Out (TDO) Transmit data is the serial data from the internal data bus that is applied through the SCI to the output line. Data format is as discussed in Data ...
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Freescale Semiconductor, Inc. 9.14.2 SCI Control Register 1 The SCI control register 1 (SCCR1), shown in functions: • • • $000E Read: Write: Reset: R8 — Bit 8 (Received) When the SCI is receiving 9-bit characters the ninth ...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) WAKE — Wakeup Method Bit This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit (MSB) position of a received character or an ...
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Freescale Semiconductor, Inc. TCIE — Transmission Complete Interrupt Enable Bit This read/write bit enables SCI interrupt requests when the TC flag becomes set. Resets clear the TCIE bit. RIE — Receiver Interrupt Enable Bit This read/write bit enables SCI interrupt ...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) RWU — Receiver Wakeup Enable Bit This read/write bit puts the receiver in a standby state. Typically, data transmitted to the receiver clears the RWU bit and returns the receiver to normal operation. ...
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Freescale Semiconductor, Inc. $0010 Read: Write: Reset: TDRE — Transmit Data Register Empty Flag This clearable, read-only flag is set when the data in the SCDR transfers to the transmit shift register. TDRE generates an interrupt request if the TIE ...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) IDLE — Receiver Idle Flag This clearable, read-only flag is set when consecutive logic 1s appear on the receiver input. IDLE generates an interrupt request if the ILIE bit in ...
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Freescale Semiconductor, Inc. 9.14.5 Baud Rate Register The baud rate register (BAUD), shown in rate for both the receiver and the transmitter. $000D Read: Write: Reset: SCP1 — SCP0–SCI Prescaler Select Bits These read/write bits control prescaling of the baud ...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) SCR2 — SCR0–SCI Baud Rate Select Bits These read/write bits select the SCI baud rate, as shown in Table Advance Information 102 For More Information On This Product, 9-2. Resets have no effect ...
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Freescale Semiconductor, Inc. Advance Information — MC68HC705C9A Section 10. Serial Peripheral Interface (SPI) 10.1 Content 10.2 10.3 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.5 10.6 10.6.1 10.6.2 10.6.3 10.2 Introduction The serial peripheral interface (SPI interface built into the ...
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 10.3 Features Features include: • • • • • • • • • 10.4 SPI Signal Description The four basic signals (MOSI, MISO, SCK, and SS) are described in the following paragraphs. Each ...
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Freescale Semiconductor, Inc. SS SCK SCK SCK SCK MISO/MOSI MSB Figure 10-1. Data Clock Timing Diagram 10.4.1 Master In Slave Out (MISO) The MISO line is configured as an input in a master device and as an output in a ...
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 10.4.3 Serial Clock (SCK) The master clock is used to synchronize data movement both in and out of the device through its MOSI and MISO lines. The master and slave devices are capable ...
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Freescale Semiconductor, Inc. 10.5 Functional Description Figure 10-2 circuitry. When a master device transmits data to a slave via the MOSI line, the slave device responds by sending data to the master device via the master’s MISO line. This implies ...
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) The SPI is double buffered on read, but not on write write is performed during data transfer, the transfer occurs uninterrupted, and the write will be unsuccessful. This condition will cause ...
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Freescale Semiconductor, Inc. 10.6 SPI Registers Three registers in the SPI provide control, status, and data storage functions. These registers are called the serial peripheral control register (SPCR), serial peripheral status register (SPSR), and serial peripheral data I/O register (SPDR) ...
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) SPE — Serial Peripheral System Enable Bit This read/write bit enables the SPI. Reset clears the SPE bit. DWOM — Port D Wire-OR Mode Option Bit This read/write bit disables the high side ...
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Freescale Semiconductor, Inc. SPR1 and SPR0 — SPI Clock Rate Selects These read/write bits select one of four master mode serial clock rates, as shown in 10.6.2 Serial Peripheral Status Register The SPI status register (SPSR), shown in signal the ...
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) SPIF set) followed by an access of the SPDR. Following the initial transfer, unless SPSR is read (with SPIF set) first, attempts to write to SPDR are inhibited. WCOL — Write Collision Bit ...
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Freescale Semiconductor, Inc. 10.6.3 Serial Peripheral Data I/O Register The serial peripheral data I/O register (SPDR), shown in used to transmit and receive data on the serial bus. Only a write to this register will initiate transmission/reception of another byte ...
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Advance Information 114 For More Information On This Product, Serial Peripheral Interface (SPI) Go to: www.freescale.com MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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Freescale Semiconductor, Inc. Advance Information — MC68HC705C9A 11.1 Contents 11.2 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.3.7 11.3.8 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.5 11.6 11.2 Introduction The MCU instruction set has 62 instructions and uses eight addressing ...
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Freescale Semiconductor, Inc. Instruction Set stored in the index register, and the low-order product is stored in the accumulator. 11.3 Addressing Modes The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways ...
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Freescale Semiconductor, Inc. 11.3.3 Direct Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the ...
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Freescale Semiconductor, Inc. Instruction Set Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). ...
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Freescale Semiconductor, Inc. 11.4 Instruction Types The MCU instructions fall into the following five categories: • • • • • 11.4.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand ...
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Freescale Semiconductor, Inc. Instruction Set 11.4.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read modify-write ...
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Freescale Semiconductor, Inc. 11.4.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to ...
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Freescale Semiconductor, Inc. Instruction Set Advance Information 122 For More Information On This Product, Table 11-3. Jump and Branch Instructions Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Branch if Equal Branch if Half-Carry Bit Clear Branch ...
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Freescale Semiconductor, Inc. 11.4.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on ...
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Freescale Semiconductor, Inc. Instruction Set 11.5 Instruction Set Summary Table 11-6. Instruction Set Summary (Sheet Source Operation Form ADC #opr ADC opr ADC opr Add with Carry ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ...
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Freescale Semiconductor, Inc. Table 11-6. Instruction Set Summary (Sheet Source Operation Form BIH rel Branch if IRQ Pin High BIL rel Branch if IRQ Pin Low BIT #opr BIT opr BIT opr Bit Test Accumulator with Memory ...
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Freescale Semiconductor, Inc. Instruction Set Table 11-6. Instruction Set Summary (Sheet Source Operation Form CLR opr CLRA CLRX Clear Byte CLR opr,X CLR ,X CMP #opr CMP opr CMP opr Compare Accumulator with Memory Byte CMP opr,X ...
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Freescale Semiconductor, Inc. Table 11-6. Instruction Set Summary (Sheet Source Operation Form JSR opr JSR opr JSR opr,X Jump to Subroutine JSR opr,X JSR ,X LDA #opr LDA opr LDA opr Load Accumulator with Memory Byte LDA ...
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Freescale Semiconductor, Inc. Instruction Set Table 11-6. Instruction Set Summary (Sheet Source Operation Form ROR opr RORA RORX Rotate Byte Right through Carry Bit ROR opr,X ROR ,X RSP Reset Stack Pointer RTI Return from Interrupt RTS ...
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Freescale Semiconductor, Inc. Table 11-6. Instruction Set Summary (Sheet Source Operation Form TAX Transfer Accumulator to Index Register TST opr TSTA TSTX Test Memory Byte for Negative or Zero TST opr,X TST ,X TXA Transfer Index Register ...
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Freescale Semiconductor, Inc. Instruction Set Advance Information 130 For More Information On This Product, Instruction Set Go to: www.freescale.com MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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Freescale Semiconductor, Inc. Advance Information — MC68HC705C9A 12.1 Contents 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 5.0-Vdc Serial Peripheral Interface Timing . . . . . . . . . . . . . . . 142 12.11 ...
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Freescale Semiconductor, Inc. Electrical Specifications 12.2 Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, ...
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Freescale Semiconductor, Inc. 12.4 Thermal Characteristics Thermal resistance plastic dual in-line (PDIP) Thermal resistance plastic leaded chip carrier (PLCC) Thermal resistance quad flat pack (QFP) Thermal resistance plastic shrink DIP (SDIP) 12.5 Power Considerations The average chip-junction temperature ...
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Freescale Semiconductor, Inc. Electrical Specifications Advance Information 134 For More Information On This Product TEST POINT C (SEE TABLE 4 Pins R1 PA7–PA0 PB7–PB0 3.26 PC7–PC0 PD5–PD0, PD7 Pins ...
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Freescale Semiconductor, Inc. 12.6 5.0-Vdc Electrical Characteristics Characteristic Output voltage I = 10.0 A oad –10.0 A oad L Output high voltage (I = –0.8 mA) PA7–PA0, PB7–PB0, PC6–PC0, oad L TCMP, PD7, PD0 (I = –1.6 ...
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Freescale Semiconductor, Inc. Electrical Specifications 12.7 3.3-Vdc Electrical Characteristics Characteristic Output voltage I = 10.0 A oad –10.0 A oad L Output high voltage (I = –0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0, oad L TCMP, PD7, PD0 (I ...
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Freescale Semiconductor, Inc 5 5. – 4.00 mA 3.00 mA 2.00 mA 1.00 mA Figure 12-2. Maximum Supply Current vs Internal Clock Frequency, V Figure 12-3. Maximum Supply Current vs Internal ...
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Freescale Semiconductor, Inc. Electrical Specifications 12.8 5.0-Vdc Control Timing Characteristic Frequency of operation Crystal External clock Internal pperating frequency (f OSC Crystal External clock Cycle time Crystal oscillator startup time Stop recovery startup time (crystal oscillator) RESET pulse width Timer ...
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Freescale Semiconductor, Inc. 12.9 3.3-Vdc Control Timing Characteristic Frequency of operation Crystal External clock Internal operating frequency (f OSC Crystal External clock Cycle time Crystal oscillator startup time Stop recovery startup time (crystal oscillator) RESET pulse width Timer (2) Resolution ...
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Freescale Semiconductor, Inc. Electrical Specifications IRQ PIN a. Edge-Sensitive Trigger Condition. The minimum pulse width (t or 250 MHz). The period t OP execute the interrupt service routine plus 19 t IRQ1 . . NORMALLY . ...
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Freescale Semiconductor, Inc. (NOTE (2) OSC1 PIN INTERNAL (3) CLOCK INTERNAL (3) ADDRESS BUS INTERNAL (3) DATA BUS RESET PIN Notes: 1. Power-on reset threshold is typically between 1 V and OSC1 line is ...
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Freescale Semiconductor, Inc. Electrical Specifications 12.10 5.0-Vdc Serial Peripheral Interface Timing No. Characteristic Operating frequency Master Slave Cycle time 1 Master Slave Enable lead time 2 Master Slave Enable lag time 3 Master Slave Clock (SCK) high time 4 Master ...
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Freescale Semiconductor, Inc. 12.11 3.3- Vdc Serial Peirpheral Interface Timing No. Characteristic Operating frequency Master Slave Cycle time 1 Master Slave Enable lead time 2 Master Slave Enable lag time 3 Master Slave Clock (SCK) high time 4 Master Slave ...
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Freescale Semiconductor, Inc. Electrical Specifications SS SS pin of master held high. (INPUT) SCK (CPOL = 0) NOTE (OUTPUT) SCK (CPOL = 1) NOTE (OUTPUT) MISO (INPUT) 10 (ref) MOSI (OUTPUT) 13 Note: This first clock edge is generated internally, ...
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Freescale Semiconductor, Inc. SS (INPUT) SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO SLAVE (OUTPUT) 6 MOSI MSB IN (INPUT) Note: Not defined but normally MSB of character just received. SS (INPUT) SCK (CPOL = ...
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Freescale Semiconductor, Inc. Electrical Specifications Advance Information 146 For More Information On This Product, Electrical Specifications Go to: www.freescale.com MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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Freescale Semiconductor, Inc. Advance Information — MC68HC705C9A 13.1 Contents 13.2 13.3 13.4 13.5 13.6 13.2 Introduction This section describes the dimensions of the plastic dual in-line package (DIP), plastic shrink dual in-line package (SDIP), plastic leaded chip carrier (PLCC), and ...
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Freescale Semiconductor, Inc. Mechanical Specifications 13.3 40-Pin Plastic Dual In-Line (DIP) Package (Case 711-03 Figure 13-1. 40-Pin Plastic DIP Package (Case 711-03) 13.4 42-Pin Plastic Shrink Dual In-Line (SDIP) Package (Case 858-01) - ...
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Freescale Semiconductor, Inc. 13.5 44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02) -N- - 0.010 (0.25) T L-M NOTES: 1.DATUMS -L-, -M-, AND -N- ARE DETERMINED WHERE TOP OF ...
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Freescale Semiconductor, Inc. Mechanical Specifications 13.6 44-Lead Quad Flat Pack (QFP) (Case 824A-01 - -D- A 0.20 (0.008 0.05 (0.002) A-B S 0.20 (0.008 -C- SEATING H G ...
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... MC order numbers for the available package Table 14-1. MC Order Numbers Package Type Ordering Information Go to: www.freescale.com Temperature Order Number Range –40°C to 85°C MC68HC705C9ACP –40°C to 85°C MC68HC705C9ACB –40°C to 85°C MC68HC705C9ACFN –40°C to 85°C MC68HC705C9ACFB Advance Information 151 ...
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Freescale Semiconductor, Inc. Ordering Information Advance Information 152 For More Information On This Product, Ordering Information Go to: www.freescale.com MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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Freescale Semiconductor, Inc. Advance Information — MC68HC705C9A A.1 Contents A.2 A.3 A.4 A.5 A.2 Introduction This section describes programming of the EPROM. A.3 Bootloader Mode Bootloader mode is entered upon the rising edge of RESET if the IRQ is at ...
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Freescale Semiconductor, Inc. EPROM Programming A.4 Bootloader Functions Three pins are used to select various bootloader functions: PD5, PD4, and PD3. Two other pins, PC6 and PC7, are used to drive the PROG LED and the VERF LED, respectively. The ...
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Freescale Semiconductor, Inc. EPGM — EPROM Program Control Bit This read/write bit controls whether the programming voltage is applied to the EPROM array. For programming, this bit can be set only if the LATCH bit has been set previously. Both ...
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Freescale Semiconductor, Inc. EPROM Programming Advance Information 156 For More Information On This Product, EPROM Programming Go to: www.freescale.com MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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Freescale Semiconductor, Inc. Advance Information — MC68HC705C9A Appendix B. M68HC05Cx Family Feature Comparisons Refer to M68HC05C Family members. MC68HC705C9A — Rev. 4.0 MOTOROLA For More Information On This Product, Table B-1 for a comparison of the features for all the ...
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Freescale Semiconductor, Inc. MC68HC705C9A — Rev. 4.0 MOTOROLA For More Information On This Product, M68HC05Cx Family Feature Comparisons Go to: www.freescale.com M68HC05Cx Family Feature Comparisons Advance Information 158 ...
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Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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Freescale Semiconductor, Inc. HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors ...