PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 161

• Manufacturer Part Number: PIC18F2480
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

14.0
The Timer3 module timer/counter incorporates these
features:
• Software selectable operation as a 16-bit timer or
• Readable and writable 8-bit registers (TMR3H
• Selectable clock source (internal or external) with
• Interrupt-on-overflow
• Module Reset on CCP special event trigger
REGISTER 14-1:
 2004 Microchip Technology Inc.
counter
and TMR3L)
device clock or Timer1 oscillator internal options
TIMER3 MODULE
bit 7
bit 6,3
bit 5-4
bit 2
bit 1
bit 0
T3CON: TIMER3 CONTROL REGISTER
bit 7
RD16: 16-bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer3 in one 16-bit operation
0 = Enables register read/write of Timer3 in two 8-bit operations
T3ECCP1:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
1x = Timer3 is the capture/compare clock source for both CCP and ECCP modules
01 = Timer3 is the capture/compare clock source for ECCP1;
00 = Timer1 is the capture/compare clock source for both CCP and ECCP modules
T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11 = 1:8 prescale value
10 = 1:4 prescale value
01 = 1:2 prescale value
00 = 1:1 prescale value
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the device clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first
0 = Internal clock (F
TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
Legend:
R = Readable bit
-n = Value at POR
R/W-0
RD16
Note 1: These bits are available on PIC18F4X80 devices only.
falling edge)
Timer1 is the capture/compare clock source for CCP1
T3ECCP1
R/W-0
(1)
OSC
PIC18F2480/2580/4480/4580
T3CKPS1 T3CKPS0 T3CCP1
/4)
R/W-0
Preliminary
W = Writable bit
‘1’ = Bit is set
R/W-0
A simplified block diagram of the Timer3 module is
shown in Figure 14-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 14-2.
The Timer3 module is controlled through the T3CON
register (Register 14-1). It also selects the clock source
options for the CCP modules (see Section 15.1.1
“CCP Modules and Timer Resources” for more
information).
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
(1)
(1)
T3SYNC TMR3CS TMR3ON
R/W-0
x = Bit is unknown
R/W-0
DS39637A-page 159
R/W-0
bit 0