MC68HC908GZ8 FREESCALE [Freescale Semiconductor, Inc], MC68HC908GZ8 Datasheet - Page 143

• Manufacturer Part Number: MC68HC908GZ8
• Description: M68HC08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

SLPAK — Sleep Mode Acknowledge
SLPRQ — Sleep Request, Go to Internal Sleep Mode
SFTRES — Soft Reset
12.13.2 MSCAN08 Module Control Register 1
LOOPB — Loop Back Self-Test Mode
Freescale Semiconductor
This flag indicates whether the MSCAN08 is in module internal sleep mode. It shall be used as a
handshake for the sleep mode request (see
bus activity while in sleep mode, it clears the flag.
This flag requests the MSCAN08 to go into an internal power-saving mode (see
Sleep
When this bit is set by the CPU, the MSCAN08 immediately enters the soft reset state. Any ongoing
transmission or reception is aborted and synchronization to the bus is lost.
The following registers enter and stay in their hard reset state:
The registers CMCR1, CBTR0, CBTR1, CIDAC, CIDAR0–CIDAR3, and CIDMR0–CIDMR3 can only
be written by the CPU when the MSCAN08 is in soft reset state. The values of the error counters are
not affected by soft reset.
When this bit is cleared by the CPU, the MSCAN08 tries to synchronize to the CAN bus. If the
MSCAN08 is not in bus-off state, it will be synchronized after 11 recessive bits on the bus; if the
MSCAN08 is in bus-off state, it continues to wait for 128 occurrences of 11 recessive bits.
Clearing SFTRES and writing to other bits in CMCR0 must be in separate instructions.
When this bit is set, the MSCAN08 performs an internal loop back which can be used for self-test
operation: the bit stream output of the transmitter is fed back to the receiver internally. The CAN
input pin is ignored and the CAN
behaves as it does normally when transmitting and treats its own transmitted message as a message
received from a remote node. In this state the MSCAN08 ignores the bit sent during the ACK slot of
the CAN frame Acknowledge field to insure proper reception of its own message. Both transmit and
receive interrupts are generated.
1 = Sleep – MSCAN08 in internal sleep mode
0 = Wakeup – MSCAN08 is not in sleep mode
1 = Sleep — The MSCAN08 will go into internal sleep mode.
0 = Wakeup — The MSCAN08 will function normally.
1 = MSCAN08 in soft reset state
0 = Normal operation
1 = Activate loop back self-test mode
0 = Normal operation
Mode).
CMCR0, CRFLG, CRIER, CTFLG, and CTCR.
Address:
Reset:
Read:
Write:
$0501
Bit 7
0
0
Figure 12-17. Module Control Register (CMCR1)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
= Unimplemented
6
0
0
TX
output goes to the recessive state (logic 1). The MSCAN08
5
0
0
12.8.1 MSCAN08 Sleep
4
0
0
3
0
0
Programmer’s Model of Control Registers
LOOPB
2
0
Mode). If the MSCAN08 detects
WUPM
1
0
12.8.1 MSCAN08
CLKSRC
Bit 0
0
RX
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