AT89C5122 ATMEL [ATMEL Corporation], AT89C5122 Datasheet - Page 135

• Manufacturer Part Number: AT89C5122
• Description: MICROCONTROLLER WITH USB AND SMART CARD READER INTERFACES
• Manufacturer: ATMEL [ATMEL Corporation]

Registers
4202D–SCR–06/05
Table 77. Serial Control Register - SCON (98h)
Reset Value = 0000 0000b (Bit addressable)
Number
FE/SM0
Bit
7
6
5
4
3
2
1
0
7
Mnemonic Description
SM0
SM1
SM2
REN
RB8
TB8
Bit
FE
RI
TI
SM1
6
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 in PCON register must be set to enable access to the FE bit
Serial port Mode bit 0 (SMOD0=1)
Refer to SM1 for serial port mode selection.
SMOD0 in PCON register must be cleared to enable access to the SM0 bit
Serial port Mode bit 1
SM0
0
0
1
1
Serial port Mode 2 bit/Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1.
This bit should be cleared in mode 0.
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8/Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the
stop bit in the other
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 66 and Figure
67 in the other modes.
SM2
5
SM1
0
1
0
1
REN
4
Mode
0
1
2
3
modes.
TB8
3
9-bit UARTVariable
DescriptionBaud Rate
Shift Register F
8-bit UARTVariable
9-bit UARTF
RB8
2
CK_IDLE
Ck_IDLE
/32 or /16
/6
1
TI
RI
0
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