AT89C5122 ATMEL [ATMEL Corporation], AT89C5122 Datasheet - Page 142

• Manufacturer Part Number: AT89C5122
• Description: MICROCONTROLLER WITH USB AND SMART CARD READER INTERFACES
• Manufacturer: ATMEL [ATMEL Corporation]

Error Conditions
Mode Fault (MODF)
Write Collision (WCOL)
Overrun Condition
SS Error Flag ( SSERR )
Interrupts
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AT8xC5122/23
sions (Figure 88). This format may be preferable in systems having only one Master and
only one Slave driving the MISO data line.
The following flags in the SPSTA signal SPI error conditions.
MODF error bit in Master mode SPI indicates that the level on the Slave Select (SS) pin
is inconsistent with the actual mode of the device. MODF is set to warn that there may
have a multi-master conflict for system control. In this case, the SPI system is affected in
the following ways:
•
•
•
When SS Disable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set
when the SS signal becomes ’0’.
However, as stated before, for a system with one Master, if the SS pin of the Master
device is pulled low, there is no way that another Master is attempting to drive the net-
work. In this case, to prevent the MODF flag from being set, software can set the SSDIS
bit in the SPCON register and therefore making the SS pin as a general-purpose I/O pin.
Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set,
followed by a write to the SPCON register. SPEN Control bit may be restored to its orig-
inal set state after the MODF bit has been cleared.
A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is
done during a transmit sequence.
WCOL does not cause an interruption, and the transfer continues uninterrupted.
Clearing the WCOL bit is done through a software sequence of an access to SPSTA
and an access to SPDAT.
An overrun condition occurs when the Master device tries to send several data bytes
and the Slave device has not cleared the SPIF bit issuing from the previous data byte
transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was
last cleared. A read of the SPDAT returns this byte. All others bytes are lost.
This condition is not detected by the SPI peripheral.
A Synchronous Serial Slave Error occurs when SS goes high before the end of a
received data in slave mode. SSERR does not cause in interruption, this bit is cleared
by writing 0 to SPEN bit ( reset of the SPI state machine ).
Two SPI status flags can generate a CPU interrupt requests:
Table 84. SPI Interrupts
Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer
has been completed. SPIF bit generates transmitter CPU interrupt requests.
An SPI receiver/error CPU interrupt request is generated.
The SPEN bit in SPCON is cleared. This disable the SPI.
The MSTR bit in SPCON is cleared.
SPIF (SP data transfer)
MODF (Mode Fault)
Flag
Request
SPI Transmitter Interrupt request
SPI Receiver/Error Interrupt Request (if SSDIS = ’0’)
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