PX1011B_11 NXP [NXP Semiconductors], PX1011B_11 Datasheet
PX1011B_11
Related parts for PX1011B_11
PX1011B_11 Summary of contents
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PX1011B PCI Express stand-alone X1 PHY Rev. 5 — 18 April 2011 1. General description The PX1011B is a high-performance, low-power, single-lane PCI Express electrical PHYsical layer (PHY) that handles the low level PCI Express protocol and signaling. The PX1011B ...
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NXP Semiconductors 2.3 JTAG interface JTAG (IEEE 1149.1) boundary scan interface Built-In Self Test (BIST) controller tests SerDes and I/O blocks at speed 3.3 V CMOS signaling 2.4 Power management Dissipates < 300 normal mode Support power ...
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NXP Semiconductors 4. Ordering information Table 2. Ordering information Type number Solder process PX1011B-EL1/G Pb-free (SnAgCu solder ball compound) PX1011B-EL1/N SnPb solder ball compound PX1011BI-EL1/G Pb-free (SnAgCu solder ball compound) [1] PX1011B-EL1/Q900 Pb-free (SnAgCu solder ball compound) [1] PX1011B-EL1/Q900 is ...
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NXP Semiconductors 6. Block diagram Fig 1. PX1011B Product data sheet TXDATA [ 7:0 ] TXCLK RXCLK Ln_TxData0 Ln_TxData1 8b/10b ENCODE PARALLEL TO SERIAL 250 MHz clock CLK GENERATOR TX I/O REFCLK I/O TX_P TX_N REFCLK_P REFCLK_N Block diagram All ...
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NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 2. Pin configuration for LFBGA81 RXIDLE SS REFCLK_P REFCLK_N RX_P RX_N ...
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NXP Semiconductors 7.2 Pin description The PHY input and output pins are described in output is defined from the perspective of the PHY. Thus a signal on a pin described as an output is driven by the PHY and a ...
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NXP Semiconductors Table 9. Symbol RXVALID PHYSTATUS RXIDLE RXSTATUS0 RXSTATUS1 RXSTATUS2 Table 10. Symbol TXCLK RXCLK REFCLK_P REFCLK_N PVT VREFS Table 11. Symbol TMS TRST_N TCK TDI TDO PX1011B Product data sheet PXPIPE interface status signals Pin Type Signaling C8 ...
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NXP Semiconductors Table 12. Symbol V DDA1 V DDA2 V DDD1 V DDD2 V DDD3 Functional description The main function of the PHY is to convert digital data into electrical signals and vice versa. The ...
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NXP Semiconductors The de-serializer or Serial-to-Parallel converter (S2P) de-serializes this data into 10-bits parallel data. Since the S2P has no knowledge about the data, the word alignment is still random. This is fixed in the digital domain by the PCS ...
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NXP Semiconductors RESET_N PHYSTATUS Fig 4. 8.5 Power management The power management signals allow the PHY to manage power consumption. The PHY meets all timing constraints provided in the PCI Express base specification regarding clock recovery and link training for ...
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NXP Semiconductors Table 13. Summary of power management state PWRDWN[1:0] Power management state 00b P0, normal operation 01b P0s, power saving state 10b P1, lower power state 11b illegal, PHY will enter P1 [1] TXIDLE = 0 [2] TXIDLE = ...
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NXP Semiconductors • The PHY continues to provide the received data on the PXPIPE interface, behaving exactly like normal data reception. • The PHY transitions from normal transmission of data from the PXPIPE interface to looping back the received data ...
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NXP Semiconductors RXDATA[7:0] RXDET_LOOPB TX_P, TX_N Fig 7. 8.8 Electrical idle The PCI Express Base Specification requires that devices send an Electrical Idle ordered-set before TX goes to the electrical idle state. The timing diagram of TXDATA[7:0] TXDATAK TX_P, TX_N ...
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NXP Semiconductors Table 14 Table 14. PWRDWN[1:0] P0: 00b P0s: 01b P1: 10b 8.9 Clock tolerance compensation The PHY receiver contains an elastic buffer used to compensate for differences in frequencies between bit rates at the two ends of a ...
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NXP Semiconductors RXDATA[7:0] RXSTATUS2, RXSTATUS1, RXSTATUS0 Fig 10. Clock correction - remove a SKP 8.10 Error detection The PHY is responsible for detecting receive errors of several types. These errors are signaled to the MAC layer using the receiver status ...
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NXP Semiconductors 8.10.1 8b/10b decode errors For a detected 8b/10b decode error, the PHY places an EDB (EnD Bad) symbol in the data stream in place of the bad byte, and encodes RXSTATUS with a decode error during the clock ...
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NXP Semiconductors RXDATA[7:0] RXSTATUS2, RXSTATUS1, RXSTATUS0 Fig 13. Elastic buffer underflow For an elastic buffer overflow, the overflow is signaled during the clock cycle where the dropped symbol would have appeared in the data stream. In the timing diagram of ...
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NXP Semiconductors 8.12 Setting negative disparity To set the running disparity to negative, the MAC asserts TXCOMP for one clock cycle that matches with the data that transmitted with negative disparity. TXDATA[7:0] TX_P, TX_N Fig 16. Setting ...
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NXP Semiconductors 9. Limiting values Table 16. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol V DDD1 V DDD2 V DDD3 DDA1 V DDA2 V ESD T stg amb [1] Human ...
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NXP Semiconductors 11. Characteristics Table 18. PCI Express PHY characteristics Symbol Parameter Supplies V digital supply voltage 1 DDD1 V digital supply voltage 2 DDD2 V digital supply voltage 3 DDD3 V supply voltage DD V analog supply voltage 1 ...
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NXP Semiconductors Table 18. PCI Express PHY characteristics Symbol Parameter dV/dt rate of change of voltage V differential input HIGH voltage IH V differential input LOW voltage IL δ duty cycle on pin REFCLK REFCLK Transmitter UI unit interval V ...
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NXP Semiconductors REFCLK+ minus REFCLK− Fig 17. Differential measurement points Table 19. PXPIPE characteristics Symbol Parameter f RXCLK frequency RXCLK f TXCLK frequency TXCLK V voltage on pin VREFS VREFS V SSTL_2 HIGH-level output voltage OH(SSTL2) V SSTL_2 LOW-level output ...
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NXP Semiconductors Fig 19. Transition eye Fig 20. Non transition eye PX1011B Product data sheet 0.6 0.5 differential 0.4 signal (V) 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 −0.6 −0.2 −0.1 0 0.1 0 °C; nominal ...
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NXP Semiconductors 12. Package outline LFBGA81: plastic low profile fine-pitch ball grid array package; 81 balls; body 1.05 mm ball A1 index area ball A1 index ...
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NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to ...
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NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...
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NXP Semiconductors Fig 22. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Appendix 14.1 Errata added 2009-09-01 The PX1011B (types PX1011B-EL1/G, PX1011BI-EL1/G, PX1011B-EL1/N and ...
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NXP Semiconductors 15. Abbreviations Table 22. Acronym BER BIST CMOS CRC EMI ESD FPGA LTSSM MAC P2S PCI PCS PHY PLL PIPE PVT S2P SerDes SKP SSTL_2 16. References [1] PCI Express Base Specification — Rev. 1.0a - PCISIG [2] ...
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NXP Semiconductors 17. Revision history Table 23. Revision history Document ID Release date PX1011B v.5 20110418 • Modifications: Table 2 “Ordering – Added type number PX1011B-EL1/Q900 – Added • Table 4 “Lead-free package • Figure 2 “Pin configuration for • ...
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NXP Semiconductors 18. Legal information 18.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Non-automotive qualified products — Unless this data sheet expressly states ...
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NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . ...