PX1011B_11 NXP [NXP Semiconductors], PX1011B_11 Datasheet - Page 7

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PX1011B_11

Manufacturer Part Number
PX1011B_11
Description
PCI Express stand-alone X1 PHY Receiver detection
Manufacturer
NXP [NXP Semiconductors]
Datasheet
NXP Semiconductors
PX1011B
Product data sheet
Table 9.
Table 10.
Table 11.
Symbol
RXVALID
PHYSTATUS
RXIDLE
RXSTATUS0
RXSTATUS1
RXSTATUS2
Symbol
TXCLK
RXCLK
REFCLK_P
REFCLK_N
PVT
VREFS
Symbol
TMS
TRST_N
TCK
TDI
TDO
PXPIPE interface status signals
Clock and reference signals
3.3 V JTAG signals
All information provided in this document is subject to legal disclaimers.
C8
D8
A2
A9
B9
C9
J2
Pin
Pin
J8
A8
B1
C1
D6
Pin
E4
F4
F3
G3
H3
output
output
output
output
output
output
input
Type
Type
input
output
input
input
-
Type
input
input
input
input
output
Rev. 5 — 18 April 2011
Signaling
SSTL_2
SSTL_2
SSTL_2
SSTL_2
SSTL_2
SSTL_2
Signaling
SSTL_2
analog I/O
Signaling
SSTL_2
PCIe I/O
PCIe I/O
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
Description
indicates symbol lock and valid data on
RX_DATA and RX_DATAK
used to communicate completion of several PHY
functions including power management state
transitions and receiver detection
indicates receiver detection of an electrical idle;
this is an asynchronous signal
encodes receiver status and error codes for the
received data stream and receiver detection (see
Table
Description
source synchronous 250 MHz transmit clock
input from MAC. All input data and signals to the
PHY are synchronized to this clock.
source synchronous 250 MHz clock output for
received data and status signals bound for the
MAC.
100 MHz reference clock input. This is the
spread spectrum source clock for PCI Express.
Differential pair input with 50 Ω on-chip
termination.
input or output to create a compensation signal
internally that will adjust the I/O pads
characteristics as PVT drifts. Connect to V
through a 49.9 Ω resistor.
reference voltage input for SSTL_2 class I
signaling. Connect to 1.25 V.
test mode select input
test clock input for the JTAG interface
test data input
test data output
Description
test reset input for the JTAG interface;
active LOW
15)
PCI Express stand-alone X1 PHY
PX1011B
© NXP B.V. 2011. All rights reserved.
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