SAK-XC2286-72F66L INFINEON [Infineon Technologies AG], SAK-XC2286-72F66L Datasheet
SAK-XC2286-72F66L
Related parts for SAK-XC2286-72F66L
SAK-XC2286-72F66L Summary of contents
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XC228x ...
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Edition 2007-02 Published by Infineon Technologies AG 81726 München, Germany © Infineon Technologies AG 2007. All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). ...
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XC228x ...
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Preliminary XC228x Revision History: V0.91, 2007-02 Previous Version(s): V0.9, 2006-11, Preliminary Page Subjects (major changes since last revision) 82 Current value numbers added to diagram 81 Wrong decimal point removed from formula 70 Description for instruction PWRDN corrected 6 Standby ...
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Preliminary Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Preliminary 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family 1 Summary of Features For a quick overview or reference, the XC228x’s properties are listed here in a condensed way. • High Performance 16-bit CPU with 5-Stage Pipeline – ...
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Preliminary – On-Chip MultiCAN Interface (Rev. 2.0B active) with 128 Message Objects (Full CAN/Basic CAN CAN Nodes and Gateway Functionality – On-Chip Real Time Clock • Mbytes External Address Space for Code and ...
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... SAK-XC2286- -40 °C to 125 °C 96F66L SAK-XC2286- -40 °C to 125 °C 72F66L SAK-XC2286- -40 °C to 125 °C 56F66L SAK-XC2285- -40 °C to 125 °C 96F66L SAK-XC2285- -40 °C to 125 °C 72F66L SAK-XC2285- -40 °C to 125 °C 56F66L 1) This Data Sheet is valid for devices starting with and including design step AA. ...
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Preliminary 2 General Device Information The XC228x derivatives are high-performance members of the Infineon XC2000 Family of full featured single-chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions (MAC unit), peripherals, ...
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Preliminary 2.1 Pin Configuration and Definition The pins of the XC228x are described in detail in functions. For explanations, please refer to the footnotes at the table’s end. summarizes all pins in a condensed way, showing their location on the ...
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Preliminary Notes to Pin Definitions 1. Ctrl.: The output signal for a port pin is selected via bitfield PC in the associated register Px_IOCRy. Output O0 is selected by setting the respective bitfield PC to 1x00 , output O1 is ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B T3OUT O1 T6OUT O2 TDO OH RxDC4B St/B EMUX1 O1 U0C1_DOUT O2 U0C0_DOUT O3 CCU62_ I CCPOS1A ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B CCU60_ St/B CC61 14 P8 St/B CCU60_ St/B CC60 16 P6 ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 21 P15.0 I ADC1_CH0 I 22 P15.1 I ADC1_CH1 I 23 P15.2 I ADC1_CH2 I T5IN I 24 P15.3 I ADC1_CH3 I T5EUD I 25 P15.4 I ADC1_CH4 I ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 35 P5.3 I ADC0_CH3 I T3IN I 39 P5.4 I ADC0_CH4 I CCU63_ I T12HRB T3EUD I TMS_A I 40 P5.5 I ADC0_CH5 I CCU60_ I T12HRB 41 P5.6 ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 47 P5.12 I ADC0_CH12 I 48 P5.13 I ADC0_CH13 I EX0BINB I 49 P5.14 I ADC0_CH14 I 50 P5.15 I ADC0_CH15 I 51 P2. St/B U0C0_ ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B TxDC0 O1 CCU63_ St/B CC61 AD14 St/B EX0AINA I 57 P11 St/B 58 P2.2 ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B TxDC2 O2 CC2_9 St/B CS1 St/B U0C1_DOUT O1 TxDC0 O2 CC2_1 ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U0C0_ O1 SELO0 U0C1_ O2 SELO1 CC2_3 St/B A19 OH U0C0_DX2D I RxDC0D St/B ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U0C1_ O1 SELO0 U0C0_ O2 SELO1 CC2_4 St/B A20 OH U0C1_DX2C I RxDC1C St/B ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U0C1_DOUT O1 TxDC1 O2 CC2_6 St/B A22 OH DIRIN I TCK_A St/B U1C0_ O1 ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 86 P10 St/B U0C0_DOUT O1 CCU60_ St/B CC61 AD1 St/B U0C0_DX0B I U0C0_DX1A St/B ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U1C1_ O1 SELO0 U1C0_ O2 SELO1 CCU61_ O3 COUT61 A4 OH U1C1_DX2A I RxDC1B I 92 TRef ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 95 P10 St/B CCU60_ O2 COUT60 AD3 St/B U0C0_DX2A I U0C1_DX2A St/B U1C1_ O1 SCLKOUT U1C0_ O2 ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U2C1_ O1 SELO0 U2C0_ O2 SELO1 U0C0_ O3 SELO4 U2C1_DX2A I RxDC4A I 100 P10 St/B U0C1_ O1 SCLKOUT CCU60_ ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 102 P0 St/B U1C1_DOUT O1 TxDC1 O2 CCU61_ O3 COUT63 A6 OH U1C1_DX0A I CCU61_ I CTRAPA U1C1_DX1B I 103 P10 St/B U0C0_DOUT ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 105 P10 St/B U0C1_DOUT O1 CCU60_ O2 COUT63 AD7 St/B U0C1_DX0B I CCU60_ I CCPOS0A RxDC4C I 106 P0 St/B ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 112 P9 St/B CCU63_ St/B CC60 113 P10 St/B U0C0_ O1 MCLKOUT U0C1_ O2 SELO0 AD8 St/B ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 116 P1 St/B CCU62_ O1 COUT62 U1C0_ O2 SELO5 U2C1_DOUT EX1BINA I U2C1_DX0C I 117 P10. St/B U0C0_ O1 SELO0 ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 120 P1 St/B CCU62_ St/B CC62 U1C0_ O2 SELO6 U2C1_ O3 SCLKOUT A10 OH CCU61_ I T12HRB EX2AINA I U2C1_DX0D I U2C1_DX1C I ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 123 P10. St/B U1C0_DOUT O1 TxDC3 O2 U1C0_ O3 SELO3 WR/WRL OH U1C0_DX0D I 124 P1 St/B CCU62_ O1 COUT63 U1C0_ O2 SELO7 ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 128 P10. St/B U1C0_ O1 SELO1 U0C1_DOUT U0C1_DX0C I RxDC3C I 129 P1 St/B CCU62_ O1 COUT61 U1C1_ O2 SELO4 ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 132 P9 St/B CCU63_ O1 COUT63 CCU63_ O2 COUT62 CCU63 _ I CTRAPA CCU60_ I CCPOS1B 133 P1 St/B CCU62_ ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 137 XTAL1 I 138 PORST I 139 ESR1 St/B EX0AINB I 140 ESR2 St/B EX1AINB I 141 ESR0 St/B 142 ...
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Preliminary Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl DDPA DDPB 36, 38, 72, 74, 108, 110, 144 37, 73, 109 1) To generate the reference clock output ...
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Preliminary 3 Functional Description The architecture of the XC228x combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a very well-balanced way. In addition, the on-chip memory blocks allow the design of compact systems-on-silicon with ...
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Preliminary 3.1 Memory Subsystem and Organization The memory space of the XC228x is configured in a von Neumann architecture, which means that all internal and external resources, such as code memory, data memory, registers and I/O ports, are organized within ...
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Preliminary This common memory space includes 16 Mbytes and is arranged as 256 segments of 64 Kbytes each, where each segment consists of four data pages of 16 Kbytes each. The entire memory space can be accessed byte wise or ...
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Preliminary 1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are word wide registers which are used for controlling and monitoring functions of the different ...
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Preliminary 3.2 External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). The EBC also controls accesses to resources connected to the on-chip LXBus (MultiCAN and the USIC modules). The LXBus ...
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Preliminary 3.3 Central Processing Unit (CPU) The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply and accumulate unit (MAC), a register-file providing ...
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Preliminary Based on these hardware provisions, most of the XC228x’s instructions can be executed in just one machine cycle which requires MHz CPU clock. For example, shift and rotate instructions are always processed during one machine ...
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Preliminary 3.4 Interrupt System With an interrupt response time of typically 8 CPU clocks (in case of internal program execution), the XC228x is capable of reacting very fast to the occurrence of non- deterministic events. The architecture of the XC228x ...
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Preliminary Table 4 XC228x Interrupt Nodes Source of Interrupt or PEC Service Request CAPCOM Register 16, or ERU Request 0 CAPCOM Register 17, or ERU Request 1 CAPCOM Register 18, or ERU Request 2 CAPCOM Register 19, or ERU Request ...
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Preliminary Table 4 XC228x Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Register CAPCOM Timer 7 CAPCOM Timer 8 A/D Converter Request 0 A/D Converter Request 1 A/D Converter Request ...
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Preliminary Table 4 XC228x Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request CAN Request 1 CAN Request 2 CAN Request 3 CAN Request 4 CAN Request 5 CAN Request 6 CAN Request 7 CAN Request 8 CAN Request ...
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Preliminary Table 4 XC228x Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request USIC2 Request 3 USIC2 Request 4 USIC2 Request 5 Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned ...
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Preliminary The XC228x also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching ...
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Preliminary 3.5 On-Chip Debug Support (OCDS) The On-Chip Debug Support system provides a broad range of debug and emulation features built into the XC228x. The user software running on the XC228x can thus be debugged within the target system environment. ...
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Preliminary 3.6 Capture/Compare Unit (CAPCOM2) The CAPCOM2 unit supports generation and control of timing sequences channels with a maximum resolution of 1 system clock cycle (8 cycles in staggered mode). The CAPCOM2 unit is typically used ...
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Preliminary register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and ...
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Preliminary T7IN T6OUF CCxIO CCxIO CCxIO T6OUF CAPCOM2 provides channels … 31. (see signals CCxIO and CCxIRQ) Figure 5 CAPCOM2 Unit Block Diagram Data Sheet Reload Reg. T7REL T7 Input Timer ...
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Preliminary 3.7 Capture/Compare Units CCU6x The XC228x features up to four CCU6 units (CCU60, CCU61, CCU62, CCU63). The CCU6 is a high-resolution capture and compare unit with application specific modes. It provides inputs to start the timers synchronously, an important ...
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Preliminary f SYS Channel 0 TxHR T12 Channel 1 Channel 2 Interrupts st art T13 Channel 3 Figure 6 CCU6 Block Diagram Timer T12 can work in capture and/or compare mode for its three channels. The modes can also be ...
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Preliminary 3.8 General Purpose Timer (GPT12E) Unit The GPT12E unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse ...
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Preliminary T3CON.BPS1 GPT T2IN T2 Mode Control T2EUD T3 T3IN Mode Control T3EUD T4IN T4 Mode Control T4EUD Figure 7 Block Diagram of GPT1 Data Sheet XC2287 / XC2286 / XC2285 XC2000 Family Derivatives Basic Clock ...
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Preliminary With its maximum resolution of 2 system clock cycles, the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock ...
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Preliminary T6CON.BPS2 GPT T5 T5IN Mode Control CAPIN CAPREL Mode Control T3IN/ T3EUD T6 Mode Control T6IN Figure 8 Block Diagram of GPT2 Data Sheet XC2287 / XC2286 / XC2285 XC2000 Family Derivatives Basic Clock GPT2 ...
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Preliminary 3.9 Real Time Clock The Real Time Clock (RTC) module of the XC228x can be clocked with a selectable clock signal from internal sources (oscillators or PLL) or external sources (pins). The RTC basically consists of a chain of ...
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Preliminary The RTC module can be used for different purposes: • System clock to determine the current time and date • Cyclic time based interrupt, to provide a system time tick independent of CPU frequency and other resources • 48-bit ...
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Preliminary 3.10 A/D Converters For analog signal measurement two 10-bit A/D converters (ADC0, ADC1) with 16 (or 8) multiplexed input channels including a sample and hold circuit have been integrated on-chip. They use the method of successive approximation. ...
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Preliminary 3.11 Universal Serial Interface Channel Modules (USIC) The XC228x features three USIC modules (USIC0, USIC1, USIC2), each providing two serial communication channels. The Universal Serial Interface Channel (USIC) module is based on a generic data shift and data storage ...
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Preliminary Target Protocols Each USIC channel can receive and transmit data frames with a selectable data word width from bits in each of the following protocols: • UART (asynchronous serial channel) – maximum baud rate: – data ...
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Preliminary 3.12 MultiCAN Module The MultiCAN module contains up to five independently operating CAN nodes with Full- CAN functionality which are able to exchange Data and Remote Frames via a gateway function. Transmission and reception of CAN frames is handled ...
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Preliminary MultiCAN Features • CAN functionality conforms to CAN specification V2.0 B active for each CAN node (compliant to ISO 11898) • five independent CAN nodes • 128 independent message objects (shared by the CAN nodes) • Dedicated ...
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Preliminary 3.13 Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, ...
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Preliminary 3.14 Clock Generation The Clock Generation Unit can generate the system clock signal high flexibility from several external or internal clock sources. • External clock signals on pad- or core-voltage level • External crystal controlled by on-chip oscillator • ...
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Preliminary 3.15 Parallel Ports The XC228x provides up to 118 I/O lines which are organized into 11 input/output ports and 2 input ports. All port lines are bit-addressable, and all input/output lines can be individually (bit-wise) configured via port control ...
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Preliminary Table 7 Summary of the XC228x’s Parallel Ports (cont’d) Port Width Alternate Functions Port 5 16 Analog input channels to ADC0, Input/Output lines for CCU6x, Timer control signals, JTAG, OCDS control, interrupts Port 6 4 ADC control lines, Serial ...
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Preliminary 3.16 Power Management The XC228x provides several means to control the power it consumes either at a given time or averaged over a certain timespan. Three mechanisms can be used (partly in parallel): • Supply Voltage Management allows the ...
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Preliminary 3.17 Instruction Set Summary Table 8 lists the instructions of the XC228x in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, ...
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Preliminary Table 8 Instruction Set Summary (cont’d) Mnemonic Description ROL/ROR Rotate left/right direct word GPR ASHR Arithmetic (sign bit) shift right direct word GPR MOV(B) Move word (byte) data MOVBS/Z Move byte operand to word op. with sign/zero extension JMPA/I/R ...
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Preliminary Table 8 Instruction Set Summary (cont’d) Mnemonic Description NOP Null operation CoMUL/CoMAC Multiply (and accumulate) CoADD/CoSUB Add/Subtract Co(A)SHR (Arithmetic) Shift right CoSHL Shift left CoLOAD/STORE Load accumulator/Store MAC register CoCMP Compare CoMAX/MIN Maximum/Minimum CoABS/CoRND Absolute value/Round accumulator CoMOV Data ...
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Preliminary 4 Electrical Parameters The operating range for the XC228x is defined by its electrical parameters. For proper operation the indicated limitations must be respected when designing a system. Attention: The parameters and values listed in the following sections of ...
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Preliminary Operating Conditions The following operating conditions must not be exceeded to ensure correct operation of the XC228x. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 10 Operating Condition Parameters Parameter Digital ...
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Preliminary Table 10 Operating Condition Parameters (cont’d) Parameter Absolute sum of overload currents External Pin Load Capacitance Voltage Regulator Buffer Capacitance Ambient temperature 1) In case both core power domains are clocked, the difference between the power supply voltages must ...
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Preliminary Parameter Interpretation The parameters listed in the following partly represent the characteristics of the XC228x and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in ...
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Preliminary 4.2 DC Parameters These parameters are static or average values, which may be exceeded during switching transitions (e.g. output current). The XC228x can operate within a wide supply voltage range from 3 5.5 V. However, during operation ...
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Preliminary 4.2.1 DC Parameters for Upper Voltage Area These parameters apply to the upper IO voltage area of 4.5 V ≤ DC Characteristics for 4.5 V ≤ Table 12 (Operating Conditions apply) Parameter Input low voltage (all except XTAL1) Input ...
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Preliminary DC Characteristics for 4.5 V ≤ Table 12 (Operating Conditions apply) Parameter XTAL1 input current 9) Pin capacitance (digital inputs/outputs) 1) Keeping signal levels within the limits specified in this table, ensures operation without overload conditions. For signal levels ...
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Preliminary 4.2.2 DC Parameters for Lower Voltage Area These parameters apply to the lower IO voltage area of 3.0 V ≤ DC Characteristics for 3.0 V ≤ Table 13 (Operating Conditions apply) Parameter Input low voltage (all except XTAL1) Input ...
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Preliminary DC Characteristics for 3.0 V ≤ Table 13 (Operating Conditions apply) Parameter XTAL1 input current 9) Pin capacitance (digital inputs/outputs) 1) Keeping signal levels within the limits specified in this table, ensures operation without overload conditions. For signal levels ...
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Preliminary 4.2.3 Power Consumption The amount of power that is consumed by the XC228x depends on several factors, such as supply voltage, operating frequency, amount of active circuitry, and operating temperature. Part of this depends on the device’s activity (switching ...
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Preliminary I [mA] DDL -50 0 Figure 12 Leakage Supply Current as a Function of Temperature Data Sheet XC2287 / XC2286 / XC2285 XC2000 Family Derivatives 50 100 82 Electrical Parameters DMP_1 ON DMP_1 off T [°C] ...
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Preliminary I [mA] DD 100 Figure 13 Supply Current in Active Mode as a Function of Frequency Data Sheet XC2287 / XC2286 / XC2285 XC2000 Family Derivatives Electrical Parameters ...
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Preliminary 4.3 Analog/Digital Converter Parameters These parameters describe how the optimum ADC performance can be reached. Table 15 A/D Converter Characteristics (Operating Conditions apply) Parameter Analog reference supply Analog reference ground Analog input voltage range Basic clock frequency Conversion time ...
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Preliminary 4) This parameter includes the sample time (also the additional sample time specified by STC), the time for determining the digital result and the time to load the result register with the conversion result. Values for the basic clock ...
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Preliminary Sample time and conversion time of the XC228x’s A/D Converters are programmable. The above timing can be calculated using f The limit values for must not be exceeded when selecting the prescaler value. ADCI Table 16 A/D Converter Computation ...
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Preliminary 4.4 AC Parameters These parameters describe the dynamic behavior of the XC228x. 4.4.1 Definition of Internal Timing The internal operation of the XC228x is controlled by the internal system clock Because the system clock signal external sources via different ...
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Preliminary The specification of the external timing (AC Characteristics) depends on the period of the system clock (TCS). Direct Drive When direct drive operation is configured (SYSCON0.CLKSEL = 11 is derived directly from the input clock signal DIRIN ...
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Preliminary The timing listed in the AC Characteristics refers to TCSs. Therefore, the timing must be calculated using the minimum TCS possible under the respective circumstances. The actual minimum value for TCS depends on the jitter of the PLL. As ...
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Preliminary Selecting and Changing the Operating Frequency When selecting a clock source and the clock generation method, the required parameters must be carefully written to the respective bitfields, to avoid unintended intermediate states. Many applications change the frequency of the ...
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Preliminary 4.4.3 External Clock Drive These parameters define the external clock supply for the XC228x. The clock signal can be supplied either to pin P2 pin XTAL1. Table 19 External Clock Drive Characteristics (Operating Conditions apply) Parameter Oscillator ...
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Preliminary 4.4.4 Testing Waveforms These references are used for characterization and production testing (except for pin XTAL1). Output delay Hold time 0.8 V DDP 0.7 V DDP 0.3 V DDP 0.2 V DDP Output timings refer to the rising edge ...
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Preliminary 4.4.5 External Bus Timing The following parameters define the behavior of the XC228x’s bus interface. Table 20 CLKOUT Reference Signal Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time 1) The CLKOUT ...
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Preliminary Variable Memory Cycles External bus cycles of the XC228x are executed in five subsequent cycle phases (AB F). The duration of each cycle phase is programmable (via the TCONCSx registers) to adapt the external bus cycles ...
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Preliminary External Bus Cycle Timing for 4.5 V ≤ Table 22 (Operating Conditions apply) Parameter Output valid delay for: RD, WR(L/H) Output valid delay for: BHE, ALE Output valid delay for: A23 … A16, A15 … A0 (on P0/P1) Output ...
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Preliminary External Bus Cycle Timing for 3.0 V ≤ Table 23 (Operating Conditions apply) Parameter Output valid delay for: RD, WR(L/H) Output valid delay for: BHE, ALE Output valid delay for: A23 … A16, A15 … A0 (on P0/P1) Output ...
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Preliminary tp CLKOUT tc 11 ALE tc 11 A23-A16, BHE, CSx RD WR(L/H) tc AD15-AD0 (read) tc AD15-AD0 (write) Figure 20 Multiplexed Bus Cycle Data Sheet High Address tc 10 ...
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Preliminary tp AB CLKOUT tc 11 ALE tc 11 A23-A0, BHE, CSx RD WR(L/H) D15-D0 (read) D15-D0 (write) Figure 21 Demultiplexed Bus Cycle Data Sheet Address ...
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Preliminary Bus Cycle Control via READY Input The duration of an external bus cycle can be controlled by the external circuitry via the READY input signal. The polarity of this input signal can be selected. Synchronous READY permits the shortest ...
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Preliminary tp CLKOUT RD, WR D15-D0 (read) D15-D0 (write) READY Synchronous READY Asynchron. Figure 22 READY Timing Note: If the READY input is sampled inactive at the indicated sampling point (“Not Rdy”) a READY-controlled waitstate is inserted (tpRDY), sampling the ...
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Preliminary External Bus Arbitration If the arbitration signals are enabled the XC228x makes its external resources available in response to an arbitration request. Bus Arbitration Timing for 4.5 V ≤ Table 24 (Operating Conditions apply) Parameter Input setup time for: ...
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Preliminary CLKOUT HOLD HLDA BREQ CSx, RD, WR(L/H) Addr, Data, BHE Figure 23 External Bus Arbitration, Releasing the Bus Notes 1. The XC228x will complete the currently running bus cycle before granting bus access. 2. This is the first possibility ...
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Preliminary CLKOUT HOLD HLDA BREQ CSx, RD, WR(L/H) Addr, Data, BHE Figure 24 External Bus Arbitration, Regaining the Bus Notes 1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the ...
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Preliminary 5 Package and Reliability In addition to the electrical parameters, the following information ensures proper integration of the XC228x into the target system. 5.1 Packaging These parameters describe the housing rather than the silicon. Table 26 Package Parameters (PG-LQFP-144) ...
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Preliminary Package Outlines 0.5 17.5 2) 0.22 ±0.05 0. 144 1 Index Marking 1) Does not include plastic or metal protrusion of 0.25 max. per side 2) Does not include dambar protrusion of 0.08 max. ...
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Preliminary 5.2 Thermal Considerations When operating the XC228x in a system, the total heat generated on the chip must be dissipated to the ambient environment to prevent overheating and resulting thermal damages. The maximum heat that can be dissipated depends ...
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Preliminary 5.3 Flash Memory Parameters The data retention time of the XC228x’s Flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the Flash memory has been erased and programmed. Table ...
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Published by Infineon Technologies AG ...