HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 318

• Manufacturer Part Number: HD6412320
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (Not Supported in the H8S/2321)
Figure 7.24 shows an example of DREQ pin falling edge activated block transfer mode transfer.
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA dead cycle ends, acceptance
resumes after the end of the dead cycle, DREQ pin low level sampling is performed again, and this
operation is repeated until the transfer ends.
Rev.6.00 Sep. 27, 2007 Page 288 of 1268
REJ09B0220-0600
φ
DREQ
Address
bus
DMA
control
Channel
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the dead cycle
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.24 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
Bus release
Idle
[1]
Request
of 2 cycles
Minimum
[2]
Request clear period
Read
[3]
Transfer source
DMA
read
Write
1 block transfer
Acceptance resumes
Transfer destination
DMA
write
Dead
[4]
Request
DMA
dead
of 2 cycles
Minimum
Idle
[5]
release
Bus
Read
[6]
Transfer source
Request clear period
DMA
read
Write
1 block transfer
Transfer destination
DMA
write
Dead
Acceptance resumes
DMA
dead
[7]
Idle
release
Bus