AT24C512B-10PU-1.8 ATMEL [ATMEL Corporation], AT24C512B-10PU-1.8 Datasheet - Page 8

• Manufacturer Part Number: AT24C512B-10PU-1.8
• Description: Two-wire Serial EEPROM 512K (65,536 x 8) with Three Device Address Inputs
• Manufacturer: ATMEL [ATMEL Corporation]

Device Addressing
Write Operations
8
AT24C512B [Preliminary]
The 512K EEPROM requires an 8-bit device address word following a start condition to
enable the chip for a read or write operation (see Figure 7 on page 9). The device
address word consists of a mandatory “1”, “0” sequence for the first four most significant
bits as shown. This is common to all two-wire EEPROM devices.
The 512K uses the three device address bits A2, A1, A0 to allow as many as eight
devices on the same bus. These bits must compare to their corresponding hardwired
input pins. The A2, A1 and A0 pins use an internal proprietary circuit that biases them to
a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read opera-
tion is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is
not made, the device will return to a standby state.
DATA SECURITY: The AT24C512B has a hardware data protection scheme that allows
the user to Write Protect the whole memory when the WP pin is at V
BYTE WRITE: A write operation requires two 8-bit data word addresses following the
device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a “0” and then clock in the first 8-bit data word. Following receipt
of the 8-bit data word, the EEPROM will output a “0”. The addressing device, such as a
microcontroller, then must terminate the write sequence with a stop condition. At this
time the EEPROM enters an internally-timed write cycle, t
All inputs are disabled during this write cycle and the EEPROM will not respond until the
write is complete (see Figure 8 on page 10).
PAGE WRITE: The 512K EEPROM is capable of 128-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not
send a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to 127
more data words. The EEPROM will respond with a “0” after each data word received.
The microcontroller must terminate the page write sequence with a stop condition (see
Figure 9 on page 10).
The data word address lower 7 bits are internally incremented following the receipt of
each data word. The higher data word address bits are not incremented, retaining the
memory page row location. When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more
than 128 data words are transmitted to the EEPROM, the data word address will “roll
over” and previous data will be overwritten. The address roll over during write is from the
last byte of the current page to the first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
ing a start condition followed by the device address word. The Read/Write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a “0”, allowing the read or write sequence to continue.
WR
, to the nonvolatile memory.
CC
.
5112A–SEEPR–8/05