M95080-DW6 STMICROELECTRONICS [STMicroelectronics], M95080-DW6 Datasheet - Page 10

• Manufacturer Part Number: M95080-DW6
• Description: 16Kbit and 8Kbit Serial SPI Bus EEPROM With High Speed Clock
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M95160, M95080
Status Register
Figure 6.
in the control logic of the device. The Status Reg-
ister contains a number of status and control bits
that can be read or set (as appropriate) by specific
instructions.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-volatile bits
of the Status Register (SRWD, BP1, BP0) become
read-only bits.
Table 3. Status Register Format
Data Protection and Protocol Control
Non-volatile memory devices can be used in envi-
ronments that are particularly noisy, and within ap-
plications that could experience problems if
memory bytes are corrupted. Consequently, the
Table 4. Write-Protected Block Size
10/40
Status Register Write Protect
SRWD
b7
Status Register Bits
BP1
0
0
1
1
shows the position of the Status Register
0
0
BP0
0
1
0
1
Block Protect Bits
Write Enable Latch Bit
0
BP1
Protected Block
Whole memory
Write In Progress Bit
Upper quarter
Upper half
BP0
none
WEL
WIP
b0
0600h - 07FFh
0400h - 07FFh
0000h - 07FFh
device features the following data protection
mechanisms:
For any instruction to be accepted, and executed,
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) for the last bit of the in-
struction, and before the next rising edge of Serial
Clock (C).
Two points need to be noted in the previous sen-
tence:
–
–
M95160
none
Write and Write Status Register instructions
are checked that they consist of a number of
clock pulses that is a multiple of eight, before
they are accepted for execution.
All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
The Block Protect (BP1, BP0) bits allow part of
the memory to be configured as read-only.
This is the Software Protected Mode (SPM).
The Write Protect (W) signal allows the Block
Protect (BP1, BP0) bits to be protected. This is
the Hardware Protected Mode (HPM).
The ‘last bit of the instruction’ can be the
eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction
(except for Read Status Register (RDSR) and
Read (READ) instructions).
The ‘next rising edge of Serial Clock (C)’ might
(or might not) be the next bus transaction for
some other device on the SPI bus.
Array Addresses Protected
Power-up
Write Disable (WRDI) instruction
completion
Write Status Register (WRSR) instruction
completion
Write (WRITE) instruction completion
0300h - 03FFh
0200h - 03FFh
0000h - 03FFh
M95080
none