M95080-DW6 STMICROELECTRONICS [STMicroelectronics], M95080-DW6 Datasheet - Page 18

• Manufacturer Part Number: M95080-DW6
• Description: 16Kbit and 8Kbit Serial SPI Bus EEPROM With High Speed Clock
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M95160, M95080
Write to Memory Array (WRITE)
As shown in
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte, address byte, and at
least one data byte are then shifted in, on Serial
Data Input (D).
The instruction is terminated by driving Chip Se-
lect (S) High at a byte boundary of the input data.
In the case of
eighth bit of the data byte has been latched in, in-
dicating that the instruction is being used to write
a single byte. The self-timed Write cycle starts,
and continues for a period t
ble 19.
in Progress (WIP) bit is reset to 0.
If, though, Chip Select (S) continues to be driven
Low, as shown in
data is shifted in, so that more than a single byte,
starting from the given address towards the end of
the same page, can be written in a single internal
Write cycle.
Figure 12. Byte Write (WRITE) Sequence
Note: Depending on the memory size, as shown in
18/40
to
S
C
D
Q
Table
Figure
Figure
23.), at the end of which the Write
Figure
12., to send this instruction to
0
12., this occurs after the
13., the next byte of input
1
High Impedance
WC
2
Instruction
3
(as specified in
4
5
Table
6
7
7., the most significant address bits are Don’t Care.
15
8
Ta-
14 13
9 10
16-Bit Address
Each time a new data byte is shifted in, the least
significant bits of the internal address counter are
incremented. If the number of data bytes sent to
the device exceeds the page boundary, the inter-
nal address counter rolls over to the beginning of
the page, and the previous data there are overwrit-
ten with the incoming data. (The page size of
these devices is 32 bytes).
The instruction is not accepted, and is not execut-
ed, under the following conditions:
–
–
–
–
3
20 21 22 23 24 25 26 27
if the Write Enable Latch (WEL) bit has not
been set to 1 (by executing a Write Enable
instruction just before)
if a Write cycle is already in progress
if the device has not been deselected, by Chip
Select (S) being driven High, at a byte
boundary (after the eighth bit, b0, of the last
data byte that has been latched in)
if the addressed page is in the region
protected by the Block Protect (BP1 and BP0)
bits.
2
1
0
7
6
5
Data Byte
4
3
28 29 30
2
1
0
31
AI01795D