M95512-W STMICROELECTRONICS [STMicroelectronics], M95512-W Datasheet
M95512-W
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M95512-W Summary of contents
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... FEATURES SUMMARY Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes) Single Supply Voltage: – 2.5 to 5.5V for M95512-W – 1.8 to 5.5V for M95512-R High Speed – 10MHz Clock Rate – 5ms Write Time Status Register Hardware Protection of the Status Register BYTE and PAGE WRITE (up to 128 Bytes) ...
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... M95512-W, M95512-R TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Serial Data Output ( Serial Data Input ( Serial Clock ( Chip Select ( Hold (HOLD Write Protect (W) ...
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... Table 10. AC Measurement Conditions Figure 15.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 11. Capacitance Table 12. DC Characteristics (M95512-W, Device Grade 6 Table 13. DC Characteristics (M95512-R Table 14. AC Characteristics (M95512-W, Device Grade Table 15. AC Characteristics (M95512-R Figure 16.Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 17.Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 18.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 19.SO8 narrow – ...
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... M95512-W, M95512-R PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 18. Ordering Information Scheme REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 19. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4/31 ( ...
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... W HOLD V SS Figure 3. SO and TSSOP Connections Figure 2. Note: See sions, and how to identify pin-1. Q Table 2. Signal Names HOLD V CC AI01789C V SS M95512-W, M95512-R M95xxx HOLD AI01790D PACKAGE MECHANICAL section for package dimen- ...
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... M95512-W, M95512-R SIGNAL DESCRIPTION During all operations, V must be held stable and CC within the specified valid range (max). CC All of the input and output signals must be held High or Low (according to voltages specified in Table OL are described next. Serial Data Output (Q). This output signal is used to transfer data serially out of the device ...
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... Serial Data Output (Q) line at a time, all the others being high impedance SPI Memory SPI Memory (2) R Device Device HOLD M95512-W, M95512 SPI Memory (2) R Device S W HOLD W HOLD AI03746e V CC ...
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... M95512-W, M95512-R SPI Modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: – CPOL=0, CPHA=0 – CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data Figure 5 ...
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... The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as Serial Clock (C) already being Low. Figure 6. also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being Low. Hold Condition M95512-W, M95512-R Table 13. Figure Hold Condition AI02029D 9/31 ...
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... M95512-W, M95512-R Status Register Figure 7. shows the position of the Status Register in the control logic of the device. The Status Reg- ister contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle ...
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... MEMORY ORGANIZATION The memory is organized as shown in Figure 7. Block Diagram HOLD W Control Logic Address Register and Counter Figure 7. High Voltage Generator I/O Shift Register Data Register 1 Page X Decoder M95512-W, M95512-R Status Register Size of the Read only EEPROM area AI01272C 11/31 ...
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... M95512-W, M95512-R INSTRUCTIONS Each instruction starts with a single-byte code, as summarized in Table 5 invalid instruction is sent (one not contained in Table 5.), the device automatically deselects it- self. 12/31 Table 5. Instruction Set Instruc Description tion WREN Write Enable WRDI Write Disable RDSR Read Status Register WRSR ...
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... The Write Enable Latch (WEL) bit, in fact, be- comes reset by any of the following events: – Power-up – WRDI instruction execution – WRSR instruction completion – WRITE instruction completion Instruction High Impedance AI03750D M95512-W, M95512-R 8., to send this instruction to 13/31 ...
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... M95512-W, M95512-R Read Status Register (RDSR) The Read Status Register (RDSR) instruction al- lows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress rec- ommended to check the Write In Progress (WIP) bit before sending a new instruction to the device ...
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... Write Status Register cycle, and is 0 when it is completed. When the cycle is com- Figure 11.. pleted, the Write Enable Latch (WEL) is reset Instruction Status Register High Impedance MSB M95512-W, M95512 AI02282D 15/31 ...
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... M95512-W, M95512-R Table 6. Protection Modes W SRWD Mode Signal Bit 1 0 Status Register is Writable Software (if the WREN instruction 0 0 Protected has set the WEL bit) (SPM) The values in the BP1 and 1 1 BP0 bits can be changed Status Register is Hardware Hardware write protected ...
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... The instruction is not accepted, and is not execut- ed Write cycle is currently in progress 16-Bit Address MSB M95512-W, M95512 Data Out 1 Data Out MSB AI01793D 17/31 ...
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... M95512-W, M95512-R Write to Memory Array (WRITE) As shown in Figure 13., to send this instruction to the device, Chip Select (S) is first driven Low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data Input (D). The instruction is terminated by driving Chip Se- lect (S) High at a byte boundary of the input data ...
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... Initial Delivery State The device is delivered with the memory array set at all 1s (FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0. M95512-W, M95512 Data Byte ...
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... M95512-W, M95512-R MAXIMUM RATING Stressing the device outside the ratings listed in Table 7. may cause permanent damage to the de- vice. These are stress ratings only, and operation of the device at these, or any other conditions out- side those indicated in the Operating sections of Table 7. Absolute Maximum Ratings ...
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... DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de- rived from tests performed under the Measure- Table 8. Operating Conditions (M95512-W) Symbol V Supply Voltage CC T ...
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... M95512-W, M95512-R Table 12. DC Characteristics (M95512-W, Device Grade 6) Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Supply Current CC Supply Current I CC1 (Standby Power mode) V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH Note: 1 ...
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... Table 14. AC Characteristics (M95512-W, Device Grade 6) Test conditions specified in Symbol Alt Clock Frequency C SCK Active Setup Time SLCH CSS1 Not Active Setup Time SHCH CSS2 Deselect Time SHSL Active Hold Time CHSH CSH t S Not Active Hold Time ...
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... M95512-W, M95512-R Table 15. AC Characteristics (M95512-R) Test conditions specified in Symbol Alt Clock Frequency C SCK Active Setup Time SLCH CSS1 Not Active Setup Time SHCH CSS2 Deselect Time SHSL Active Hold Time CHSH CSH t S Not Active Hold Time ...
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... Figure 16. Serial Input Timing S tCHSL C tDVCH D High Impedance Q Figure 17. Hold Timing HOLD tSLCH tCHSH tCHDX tCLCH MSB IN tHLCH tCLHL tHLQZ M95512-W, M95512-R tSHSL tSHCH tCHCL LSB IN AI01447C tHHCH tCLHH tHHQV AI01448B 25/31 ...
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... M95512-W, M95512-R Figure 18. Output Timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D 26/31 tCH tCLQV tQLQH tQHQL tCL tSHQZ LSB OUT AI01449D ...
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... millimeters Min. Max. 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 – – 5.80 6.20 0.25 0.50 0.40 0.90 0° 8° 8 0.10 M95512-W, M95512 45˚ inches Typ. Min. 0.053 0.004 0.013 0.007 0.189 0.150 0.050 – 0.228 0.010 0.016 0° 8 Max. 0.069 0.010 0.020 0.010 0.197 0.157 – 0.244 0.020 0.035 8° ...
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... M95512-W, M95512-R Figure 20. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline A CP Note: 1. Drawing is not to scale. Table 17. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data Symbol Typ 1.000 3.000 e 0.650 E 6.400 E1 4.400 L 0.600 L1 1.000 28/ ...
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... Lead-Free and RoHS compliant Note: 1. Ordering information related to the M95512 identified with the process letter "A". For a list of available options (speed, package, etc.) or for further information on any aspect of this (1) M95512 – device, please contact your nearest ST Sales Of- fice. M95512-W, M95512 29/31 ...
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... Document status changed to Preliminary Data. Updated Figure 4., Bus Master and Memory Devices on the SPI Bus Timing. Power On Reset 4., Write-Protected Block 30-Jun-2005 6.0 7., Absolute Maximum 12., DC Characteristics (M95512-W, Device Grade Characteristics 30/31 Description of Revision added. AEC-Q100-002 compliance. Device Grade information clarified. and t corrected CHHH ...
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