TC55VBM316AFTN TOSHIBA [Toshiba Semiconductor], TC55VBM316AFTN Datasheet

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TC55VBM316AFTN

Manufacturer Part Number
TC55VBM316AFTN
Description
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
Manufacturer
TOSHIBA [Toshiba Semiconductor]
Datasheet

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TENTATIVE
524,288-WORD BY 16-BIT/1,048,576-WORD BY 8-BIT FULL CMOS STATIC RAM
DESCRIPTION
words by 16 bits/1,048,576 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this
device operates from a single 2.3 to 3.6 V power supply. Advanced circuit technology provides both high speed and
low power at an operating current of 3 mA/MHz and a minimum cycle time of 40 ns. It is automatically placed in
low-power mode at 0.7 µA standby current (at V
high or (CE2) is asserted low. There are three control inputs. CE1 and CE2 are used to select the device and for
data retention control, and output enable ( OE ) provides fast memory access. Data byte control pin ( LB , UB )
provides lower and upper byte access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. And, with a guaranteed operating extreme
temperature range of −40° to 85°C, the TC55VBM316AFTN/ASTN can be used in environments exhibiting extreme
temperature conditions. The TC55VBM316AFTN/ASTN is available in a plastic 48-pin thin-small-outline package
(TSOP).
FEATURES
PIN ASSIGNMENT
The TC55VBM316AFTN/ASTN is a 8,388,608-bit static random access memory (SRAM) organized as 524,288
Low-power dissipation
Operating: 9 mW/MHz (typical)
Single power supply voltage of 2.3 to 3.6 V
Power down features using CE1 and CE2
Data retention supply voltage of 1.5 to 3.6 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of −40° to 85°C
Standby Current (maximum):
48 PIN TSOP
Pin Name
Pin Name
Pin Name
Pin No.
Pin No.
Pin No.
3.6 V
3.0 V
24
1
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
I/O3 I/O11
A15
A17
17
33
1
10 µA
5 µA
(Normal)
A14
A7
18
34
(TOP VIEW)
2
A13
I/O4 I/O12 V
19
A6
35
3
A12
A5
20
36
4
48
25
A11
A4
21
37
DD
5
I/O5
A10
DD
A3
22
38
6
= 3 V, Ta = 25°C, typical) when chip enable ( CE1 ) is asserted
I/O13 I/O6
A9
23
A2
39
7
A8
A1
24
40
8
Access Times (maximum):
Package:
TSOPⅠ48-P-1220-0.50 (AFTN) (Weight:0.51 g typ)
TSOPⅠ48-P-1214-0.50 (ASTN) (Weight:0.36 g typ)
Access Time
CE2
CE
OE
I/O14 I/O7
TC55VBM316AFTN/ASTN40,55
NC
A0
25
41
9
1
PIN NAMES
*: OP pin must be open or connected to GND.
Access Time
Access Time
Access Time
I/O1~I/O16
CE , CE2
CE
LB , UB
NC
A-1~A18
A0~A18
10
26
42
BYTE
GND
R/W
V
OP*
1
1
OE
NC
DD
I/O15 I/O8
GND
R/W
27
43
11
Address Inputs (Word Mode)
Address Inputs (Byte Mode)
Chip Enable
Read/Write Control
Output Enable
Data Byte Control
Data Inputs/Outputs
Byte (×8 mode) Enable
Power
Ground
No Connection
Option
CE2
OE
12
28
44
TC55VBM316AFTN/ASTN
40 ns
40 ns
40 ns
25 ns
40
I/O16
I/O1
/A-1
OP
2002-08-05 1/15
13
29
45
GND
I/O9
UB
14
30
46
BYTE
I/O2 I/O10
LB
15
31
47
55 ns
55 ns
55 ns
30 ns
55
A18
A16
16
32
48

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TC55VBM316AFTN Summary of contents

Page 1

... This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating extreme temperature range of −40° to 85°C, the TC55VBM316AFTN/ASTN can be used in environments exhibiting extreme temperature conditions. The TC55VBM316AFTN/ASTN is available in a plastic 48-pin thin-small-outline package (TSOP) ...

Page 2

... A18 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 CE 1 CE2 LB UB R/W OE BYTE TC55VBM316AFTN/ASTN40,55 MEMORY CELL ARRAY 4,096 × 128 × 16 (8,388,608) SENSE AMP COLUMN ADDRESS DECODER COLUMN ADDRESS REGISTER COLUMN ADDRESS BUFFER CLOCK GENERATOR A GND CE A5 A16 ...

Page 3

... V when measured at a pulse width of 20ns DC RECOMMENDED OPERATING CONDITIONS ( SYMBOL V Power Supply Voltage DD V Input High Voltage IH V Input Low Voltage IL V Data Retention Supply Voltage DH *: −2.0 V when measured at a pulse width of 20ns TC55VBM316AFTN/ASTN40,55 R/W BYTE LB UB I/O1~I/ Output * * Output ...

Page 4

... CE2 = 0.2 V (at BYTE ≥ DDS2 ( 25° MHz) CAPACITANCE SYMBOL PARAMETER C Input Capacitance IN C Output Capacitance OUT Note: This parameter is periodically sampled and is not 100% tested. TC55VBM316AFTN/ASTN40, 2 TEST CONDITION = 0 V − CE2 = ...

Page 5

... TC55VBM316AFTN/ASTN UNIT 40 55 MIN MAX MIN MAX            ...

Page 6

... TC55VBM316AFTN/ASTN UNIT 40 55 MIN MAX MIN MAX            ...

Page 7

... DD 90% 10% GND 1 V/ BYTE FUNCTION SYMBOL t BYTE Setup Time BS t BYTE Recovery Time BR TIMING DIAGRAMS BYTE CE2 CE 1 BYTE TC55VBM316AFTN/ASTN40,55 Fig.2 : Output load 90% 10 PARAMETER TEST CONDITION × 0 0 ns(Fig.1) × 0 × 0 TTL Gate(Fig.2) ...

Page 8

... OUT I/O1~16 (Word Mode) Hi-Z I/O1~8 (Byte Mode) WRITE CYCLE 1 (R/W CONTROLLED) Address A0~A18 (Word Mode) A-1~A18 (Byte Mode) R CE2 OUT I/O1~16 (Word Mode) I/O1~8 (Byte Mode I/O1~16 (Word Mode) I/O1~8 (Byte Mode) TC55VBM316AFTN/ASTN40, ACC t CO1 t CO2 OEE t COE (See Note ...

Page 9

... IN I/O1~16 (Word Mode) I/O1~8 (Byte Mode) WRITE CYCLE 3 (CE2 CONTROLLED) Address A0~A18 (Word Mode) A-1~A18 (Byte Mode) R CE2 OUT I/O1~16 (Word Mode) I/O1~8 (Byte Mode I/O1~16 (Word Mode) I/O1~8 (Byte Mode) TC55VBM316AFTN/ASTN40,55 (See Note ODW Hi-Z t COE ...

Page 10

... If CE1 ( goes HIGH(or CE2 goes LOW) coincident with or before R/W goes HIGH, the outputs will remain at high impedance. ( HIGH during the write cycle, the outputs will remain at high impedance. (5) Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. TC55VBM316AFTN/ASTN40,55 (See Note 4) CONTROLLED ...

Page 11

... GND CONTROLLED DATA RETENTION MODE 2 GND TC55VBM316AFTN/ASTN40, − − − − 40° to 85°C PARAMETER = 3 −40~85° −40~40° −40~85°C (See Note 1) DATA RETENTION MODE (See Note 2) t CDR − 0.2 V ...

Page 12

... V or CE1 ≥ V − 0.2 V, CE2 ≤ 0 CE2 ≥ (5) When UB ( operating at the V the transition of V from 2.3(2.7) to 2.2V(2.4 V). DD TC55VBM316AFTN/ASTN40,55 (min.) level, the operating current is given − 0 (min.) level, the operating current is given during the DDS1 ...

Page 13

... PACKAGE DIMENSIONS TSOPⅠ48-P-1220-0. Weight:0.51 g (typ) TC55VBM316AFTN/ASTN40,55 18.4 0.1 20.0 0.2 Unit: 1.0 0.1 0.1 0.05 1.2max 0.5 0.1 2002-08-05 13/15 ...

Page 14

... PACKAGE DIMENSIONS TSOPⅠ48-P-1214-0. Weight:0.36 g (typ) TC55VBM316AFTN/ASTN40, 12.4 0.1 14.0 0.2 Unit:mm 1.0 0.1 0.1 0.05 1.2max 0.5 0.1 2002-08-05 14/15 ...

Page 15

... TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. TC55VBM316AFTN/ASTN40,55 2002-08-05 15/15 000707EBA ...

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