IS24C128-2 ISSI [Integrated Silicon Solution, Inc], IS24C128-2 Datasheet
IS24C128-2
Related parts for IS24C128-2
IS24C128-2 Summary of contents
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... Low Power CMOS Technology – Active Current less than 2 mA (5V) – Standby Current less than 5 µA (5V) – Standby Current less than 2 µA (2.5V) • Low Voltage Operation – IS24C128-2: Vcc = 1.8V to 5.5V – IS24C128-3: Vcc = 2.5V to 5.5V • 400 KHz ( Protocol) Compatibility • Hardware Data Protection – ...
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... IS24C128 FUNCTIONAL BLOCK DIAGRAM Vcc SDA SCL WP SLAVE ADDRESS REGISTER & COMPARATOR GND nMOS 2 CONTROL LOGIC WORD ADDRESS COUNTER ACK Integrated Silicon Solution, Inc. — www.issi.com — ISSI HIGH VOLTAGE GENERATOR, TIMING & CONTROL EEPROM ARRAY Y DECODER Clock > DATA DI/O REGISTER 1-800-379-4774 PRELIMINARY INFORMATION Rev ...
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... IS24C128 PIN CONFIGURATION 8-Pin DIP and SOIC GND 4 5 PIN DESCRIPTIONS A0-A1 Address Inputs SDA Serial Address/Data I/O SCL Serial Clock Input WP Write Protect Input Vcc Power Supply NC No Connect GND Ground SCL This input clock pin is used to synchronize the data transfer to and from the device ...
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... After a successful data transfer, each receiving device is required to generate an ACK. The Acknowledging device pulls down the SDA line. Reset The IS24C128 contains a reset function in case the 2- wire bus transmission is accidentally interrupted (eg. a power loss), or needs to be terminated mid-stream. The reset is caused when the Master device creates a Start condition ...
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... IS24C128 initiates the internal Write cycle. ACK polling can be initiated immediately. This involves issuing the Start condition followed by the Slave address for a Write operation. If the IS24C128 is still busy with the Write operation, no ACK will be returned. If the IS24C128 has completed the Write operation, an ACK will be returned and the host can then proceed with the next Read or Write operation ...
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... Figure 2. Output Acknowledge SCL from Master Data Output from Transmitter Data Output from Receiver Figure 3. Start and Stop Conditions SCL SDA 6 Vcc Master IS24C128 Transmitter/ Receiver Integrated Silicon Solution, Inc. — www.issi.com — ISSI ® ACK 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00B ...
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... IS24C128 Figure 4. Data Validity Protocol SCL SDA Figure 5. Slave Address BIT Figure 6. Byte Write Device R Address T SDA Bus Activity Figure 7. Page Write Device R T Word Address (n) Address T E SDA A Bus Activity R/W Integrated Silicon Solution, Inc. — www.issi.com — ...
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... IS24C128 Figure 8. Current Address Read Activity Figure 9. Random Address Read Device R T Address T E SDA A Bus C K Activity R/W DUMMY WRITE Figure 10. Sequential Read R E Device A Address D SDA A Bus C Activity K R Device A T Address ...
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... This is a stress rating only. Functional operation of the device outside these conditions or those indicated in the operational sections of this specification is not implied. Exposure to these conditions for extended periods may affect reliability. OPERATING RANGE (IS24C128-2) Range Ambient Temperature Commercial 0° ...
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... IS24C128 DC ELECTRICAL CHARACTERISTICS Commercial ( + Symbol Parameter V Output Low Voltage Output Low Voltage Input High Voltage IH V Input Low Voltage IL I Input Leakage Current LI I Output Leakage Current LO Notes: V min and V max are reference only and are not tested. ...
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... IS24C128 AC WAVEFORMS Figure 11. Bus Timing t R SCL t SU:STA SDA IN SDA OUT WP Figure 12. Write Cycle Timing SCL 8th BIT SDA WORD n Integrated Silicon Solution, Inc. — www.issi.com — PRELIMINARY INFORMATION Rev. 00A 03/11/ HIGH LOW t HD:DAT t t HD:STA SU:DAT ...
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... Plastic DIP (8-pin) IS24C128-3G Small Outline (JEDEC STD) (8-pin) IS24C128-3Z TSSOP (14-pin) Part Number Package IS24C128-3PI 300-mil Plastic DIP (8-pin) IS24C128-3GI Small Outline (JEDEC STD) (8-pin) IS24C128-3ZI TSSOP (14-pin) Integrated Silicon Solution, Inc. — www.issi.com — ISSI ® ISSI ® ...