TLE5011_11 INFINEON [Infineon Technologies AG], TLE5011_11 Datasheet
TLE5011_11
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TLE5011_11 Summary of contents
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TLE5011 GMR Angle Sensor Data Sheet ...
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Edition 2011-03 Published by Infineon Technologies AG 81726 Munich, Germany 2011 Infineon Technologies AG © All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With ...
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Revision History: 2011-03, V2.0 Previous Revision: V1.0 Page Subjects (major changes since last revision) 6 Ordering code updated 7 Section 1.2 updated 14 Table 3, supply voltage and magnetic induction expanded; figure 7 added 15 Table 4; notes of supply ...
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Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SSC Baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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GMR Angle Sensor 1 Product Description 1.1 Overview The TLE5011 is a 360° angle sensor that detects the orientation of a magnetic field by measuring sine and cosine angle components with monolithic integrated Giant Magneto Resistance (iGMR) elements. Data communications ...
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Features • Giant Magneto Resistance (GMR)-based principle • Integrated magnetic field sensing for angle measurement • Designed for 3.3 V and 5 V systems • Full 0 - 360° angle measurement • Highly accurate single-bit SD-ADC • 16-bit representation ...
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Functional Description 2.1 General The GMR angle sensor is implemented in vertical integration. This means that the GMR active areas are integrated above the logic portion of the TLE5011 device. GMR elements change their resistance depending on the direction ...
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V 0° Figure 2 Ideal Output of the GMR Angle Sensor 2.2 Pin Configuration Figure 3 Pin Configuration (Top View) 2.3 Pin Description Table 1 Pin Describtion Pin No. Symbol 1 CLK 2 SCK DATA 5 TST1 ...
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Block Diagram The block diagram shows all switches in the reset position. GND GND-off Comp VRG VRG_OV GMR X VDDG GND VDDG GND GMR Y 2 differential TST1 TST 2 Figure 4 Block Diagram Final Data Sheet VDD VDD_OV ...
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Functional Block Description 2.5.1 Internal Power Supply The internal stages of the TLE5011 are supplied with different voltage regulators: • GMR Voltage Regulator VRG • Analog Voltage Regulator VRA • Digital Voltage Regulator VRD Each voltage regulator has its ...
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Safety Features The TLE5011 has a multiplicity on safety features to support Safety Integrity Level (SIL). Sensors meeting this performance standard are identified by Infineon with the following logo: Figure 5 PRO SIL Logo Safety features are: • Angle ...
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Specification 3.1 Application Circuit The application circuit shows the microcontroller version with open-drain capabilities. 12V CAN RX CAN Tranceiver CAN TX GND Figure 6 Application Circuit A complete system may consist of one TLE5011 and a microcontroller. The second ...
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Operating Range To ensure correct operation of the TLE5011, the operating conditions identified in All parameters specified in the following sections refer to these operating conditions, unless otherwise indicated. Table 3 is valid for -40°C < T < 150°C ...
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Note: The thermal resistances listed in the corresponding ambient temperature. Calculation of the Junction Temperature The total power dissipation P of the chip increases its temperature above the ambient temperature. TOT The power multiplied by the total thermal resistance is ...
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Table 4 Electrical Parameters Parameter Symbol Input Signal V L Low Level Input Signal V H High Level Capacitance of SSC C LDATA Data Pin 1) Without external pull-up resistor for SSC interface 2) Not subject to production test - ...
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ESD Protection Table 7 ESD Protection Parameter ESD Voltage 1) Human Body Model (HBM) according to: AEC-Q100-002 2) Socketed Device Model (SDM) according to: ESDA/ANSI/ESD SP5.3.2-2008 3.4.3 GMR Parameters All parameters apply over the full operating range, unless otherwise ...
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Offset Definition The offset of the X and Y signals is defined as the mean value between the signed maximum and minimum values of the idealized sine or cosine wave. Amplitude Definition The amplitude is defined as half the difference ...
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Calibration GMR Values The end-of-line calibration can be accomplished using following sequence: 1. Turn magnetic field 360° left and measure X and Y values 2. Calculate amplitude, offset, phase correction values of left turn 3. Turn further 90° left ...
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Offset value at 25°C in digits Temperature value at 25°C in digits Temperature value in digits S : Sensitivity of the temperature measurement path, (see T Offset ...
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GMR Parameters after Calibration After calibration under the conditions specified in the sensor has a remaining error as shown in The error value refers and operating conditions given in Z Table 10 GMR Parameter ...
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Clock Supply (CLK Timing Definition) The clock signal input “CLK” must fulfill certain requirements described in this section: • The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse width ...
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Master) Shift Register Clock Generator Figure 10 SSC Half-Duplex Configuration - Microcontroller with Open Drain µC (SSC Master) Shift Register Clock Generator Figure 11 SSC Half-Duplex Configuration - Microcontroller without Open Drain 3.9.1 SSC Timing Definition SSC Timing ...
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DATA Write Time ( t ) DATW During this time, the TLE5011 changes the data line, so the data are invalid. The DATA Write Time values are defined without a pull-up resistor. Pull-up Time Value ( The ...
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The margin time shown in Table 14 sample read of the TLE5011 itself for read-back useful to have a maximum distance between the WRITE and subsequent READ. This ensures a reliable read- back of the written data for ...
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SCK (PAD) Suppressed Spike SCK Fall SCK Rise Figure 14 SSC Spike Filter Filter for DATA and CS The following conditions apply: • The DATA pin has a ’2-of-3’ filter • The CS input has a ’2-of-3’ filter that suppresses ...
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Register Table This section describes the complete address range as well as all registers of the TLE5011. It also defines the read/write access rights of the specific registers. registers is accomplished via the SSC interface. Table 16 Address Map Name ...
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Abbreviation Function S Status R Read W Write CTRL1 Addr reserved reserved reserved - - Field Bits reserved 7 reserved 6 reserved 5 reserved 4 SSC_FILT 3 reserved 2 AUTO The values in ...
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Y_L Addr Y_H Addr FCNT_STAT Addr reserved STAT_VR GMR_OFF - R S Field Bits Type reserved 7 - STAT_VR 6 RS GMR_OFF 5 RU UPDATE 4 RU FCNT ...
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FSYNC_INV Addr FILT_INV WU Field Bits FILT_INV 7 FSYNC 6-0 ANGT Addr reserved ANGT_EN - W Field Bits reserved 7 - ANGT_EN 6 ANGT_Y 5-3 ANGT_X 2-0 Reserved Registers ( ...
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Reserved Addr TST Addr TEMP_EN ADCPY FILT_PAR Field Bits TEMP_EN 7 ADCPY 6 FILT_PAR 5 FILT_CRS 4 FIR_BYP 3 1) TST_ADC 2 1) TST_GMR 1 ...
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ID Addr DEV_ID R Field Bits DEV_ID 7-4 reserved 3-0 LOCK Addr Field Bits LOCK 7-0 CTRL2 Addr VDD_OV VDD_OFF GND_OFF Field Bits VDD_OV ...
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Field Bits VRA_OV 3 VRD_OV 2 S_NO 1-0 3.9.6 Data Communication via SSC Data communication via the SSC interface has the following characteristics: • The data transmission order is “Most Significant Bit (MSB) first”. • Data is put on the ...
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CRC Generation These are the requirements for CRC generation: • This CRC is defined according to the J1850 Bus-Specification of 15.Feb.1994 for Class B Data Communication. • Every new transfer resets the CRC generation. • Every Byte of a ...
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Example1: CRC calculation (Update X and Y and set ADC-Test Mode) Command Data CRC (init all ‘0’) 00000001 00000101 00000000 ----------------------------------- xor 11111111 -------- =11111110.0 . xor 10001110.1 . --------.- . = 01110000.10 . xor 1000111.01 . -------.-- . = ...
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Example2: Use of two TLE5011 units in a bus mode. Table 17 Update X,Y of two TLE5011 units, and read first TLE5011 SSC Byte no. Description 1) 1 Command 2) 2 Command 3 Data Byte Data ...
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Test Structures Two different test signal structures are implemented in the TLE5011: • Functional Angle Test. In this case, well-known signals feed the ADCs. • Temperature Measurement. This is useful to read out the chip temperature for compensation purposes. ...
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ADC Test Vectors Figure 17 ADC Test Vectors 3.10.2 Temperature Measurement An internal bandgap voltage can be used to measure the temperature on the chip. This may be used to compensate for temperature-dependent errors. The temperature values is sent out ...
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Functional Angle Test and Temperature Measurement Timing The functional angle test and the temperature readout are based on the same mechanism. In the Normal Mode, the output path is linked to the functional angle test or to the temperature ...
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Overvoltage Comparators Various comparators monitor the voltage in order to ensure error-free operation. The overvoltages must be active for at least t works as digital spike suppression. Table 20 Test Comparators Parameter Symbol Overvoltage Detection V OVG V OVA ...
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V TST1 GND Figure 21 GND-off Comparator 3.11 off Comparator DD The V -off Comparator detects a disconnection of the V DD supplied by the SCK, CLK and CS input pins via the ESD structures. It activates ...
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Package Information 4.1 Package Parameters Table 21 Package Parameters Parameter Symbol Thermal Resistance R thJA R thJC R thJL Soldering Moisture Level Lead frame Plating 1) According to Jedec JESD51-7 Package Outline PG-DSO-8 Figure 23 PG-DSO-8 Package Dimension Final ...
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Figure 24 Position of Sensing Element Footprint PG-DSO-8 Figure 25 Footprint PG-DSO-8 Packing Figure 26 Tape and Reel Final Data Sheet 0.65 1.27 8 0.3 1.75 6.4 2.1 43 TLE5011 Package Information V2.0, 2011-03 ...
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Marking Position Marking 1st Line 5011xx 2nd Line xxx 3rd Line Gxxxx Processing Note: For processing recommendations, please refer to Infineon’s Notes on Processing Final Data Sheet Description See ordering table on page 6 Lot code G .. green, 4-digit ...
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Published by Infineon Technologies AG ...