MCF51AC128A FREESCALE [Freescale Semiconductor, Inc], MCF51AC128A Datasheet - Page 7

• Manufacturer Part Number: MCF51AC128A
• Description: MCF51AC256 ColdFire Microcontroller
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor
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Flexible timer/pulse-width modulators (FTM)
— 16-bit Free-running counter or a counter with initial and final value. The counting can be up and unsigned, up and
— Up to 6 channels, and each channel can be configured for input capture, output compare or edge-aligned PWM
— The load of the FTM registers which have write buffer can be synchronized; write protection for critical registers
— Generation of the triggers to ADC (hardware trigger)
— A fault input for global fault control
— Backwards compatible with TPM
Timer/pulse width modulator (TPM)
— 16-bit free-running or modulo up/down count operation
— Two channels, each channel may be input capture, output compare, or edge-aligned PWM
— One interrupt per channel plus terminal count interrupt
Cyclic redundancy check (CRC) generator
— High speed hardware CRC generator circuit using 16-bit shift register
— CRC16-CCITT compliancy with x
— Error detection for all single, double, odd, and most multi-bit errors
— Programmable initial seed value
Analog comparators (ACMP)
— Full rail to rail supply operation
— Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output
— Option to compare to fixed internal bandgap reference voltage
— Option to allow comparator output to be visible on a pin, ACMPxO
Inter-integrated circuit (IIC)
— Compatible with IIC bus standard
— Multi-master operation
— Software programmable for one of 64 different serial clock frequencies
— Interrupt driven byte-by-byte data transfer
— Arbitration lost interrupt with automatic mode switching from master to slave
— Calling address identification interrupt
— Bus busy detection
— 10-bit address extension
Controller area network (CAN)
— Implementation of the CAN protocol — Version 2.0A/B
— Five receive buffers with FIFO storage scheme
— Three transmit buffers with internal prioritization using a “local priority” concept
signed, or up-down and unsigned
mode, all channels can be configured for center-aligned PWM mode
– Channels can operate as pairs with equal outputs, pairs with complimentary outputs or independent channels
– Each pair of channels can be combined to generate a PWM signal (with independent control of both edges of
– Deadtime insertion is available for each complementary pair
– Standard and extended data frames
– Zero to eight bytes data length
– Programmable bit rate up to 1 Mbps
– Support for remote frames
(with independent outputs)
PWM signal)
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Preliminary—Subject to Change Without Notice
16
+ x
12
+ x
5
+ 1 polynomial
MCF51AC256 Family Configurations
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