MCF5485 FREESCALE [Freescale Semiconductor, Inc], MCF5485 Datasheet

Page 1

... Data Sheet: Technical Data MCF5485 Integrated Microprocessor Electrical Characteristics This chapter contains electrical specification tables and reference timing diagrams for the MCF5485 microprocessor. This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of the MCF5485. MCF548X Family Features: • ColdFire V4e Core – ...

Page 2

... Watchdog Timer Slice Timers Timers x 4 FlexCAN x 2 DSPI 1 Available in MCF5485, MCF5484, MCF5483 and MCF5482 devices. 2 Available in MCF5485, MCF5484, MCF5481 and MCF5480 devices. 3 Available in MCF5485, MCF5483, and MCF5481 devices. MCF5485 Integrated Microprocessor Electrical Characteristics, Rev DDR SDRAM PLL Interface ...

Page 3

... Figure 10.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 11.FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 12.FlexBus Write Timing . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 13.SDR Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 14.SDR Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MCF5485 Integrated Microprocessor Electrical Characteristics, Rev Table of Contents Figure 15.DDR Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . 18 Figure 16.DDR Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 17.DDR Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 18 ...

Page 4

... This published maximum operating ambient temperature should be used only as a system design guideline. All device operating parameters are guaranteed only when the junction temperature lies within the specified range. MCF5485 Integrated Microprocessor Electrical Characteristics, Rev Table 1. Absolute Maximum Ratings Symbol ...

Page 5

... USB digital logic operation voltage range USB PHY operation voltage range USB oscillator analog operation voltage range USB PLL operation voltage range Input high voltage SSTL 3.3V/2.5V MCF5485 Integrated Microprocessor Electrical Characteristics, Rev. 3 Freescale Semiconductor Table 3. Thermal Resistance Four layer board (2s2p) Four layer board (2s2p) — ...

Page 6

... To further enhance noise isolation, an external filter is strongly recommended for PLL analog V Figure 2 should be connected between the board V close to the dedicated PLL V pin as possible. DD Board V DD 4.2 Supply Voltage Sequencing and Separation Cautions Figure 3 shows situations in sequencing the I MCF5485 Integrated Microprocessor Electrical Characteristics, Rev Symbol should have a filtered input ...

Page 7

... Drop IV /PLL Drop EV /SD V supplies DD DD MCF5485 Integrated Microprocessor Electrical Characteristics, Rev. 3 Freescale Semiconductor Supplies Stable 2 is non-critical during power-up and power-down sequences 0V, the sense circuits in the I/O pads cause all pad output drivers connected ...

Page 8

... The ground pin of the A USB receptacles for downstream ports should also be connected to the board ground plane, but industry practice varies widely on the connection of the shield of the A USB receptacles to other system grounds. Take precautions for control of ground loops between hosts and self-powered USB devices through the cable shield. MCF5485 Integrated Microprocessor Electrical Characteristics, Rev MCF548x (5V) (3 ...

Page 9

... Pin DD USBVDD (Bias generator supply) USB_PHYVDD (Main transceiver supply) USB_PLLVDD (PLL supply) USB_OSCVDD (Oscillator supply) USB_OSCAVDD (Oscillator analog supply) MCF5485 Integrated Microprocessor Electrical Characteristics, Rev. 3 Freescale Semiconductor and each of the USB V pins pin, a total of five circuits GND Figure 6. USB V ...

Page 10

... DSPI (DSPISOUT, DSPICS0/SS, DSPICS[2:3], DSPICS5/PCSS) PCI (PCIAD[31:0], PCIBG[4:1], PCIBG0/PCIREQOUT, PCIDEVSEL, PCICXBE[3:0], PCIFRM, PCIPERR, PCIRESET, PCISERR, PCISTOP, PCIPAR, PCITRDY, PCIIRDY I2C (SCL, SDA) BDM (PSTCLK, PSTDDATA[7:0], DSO/TDO, RSTO MCF5485 Integrated Microprocessor Electrical Characteristics, Rev USBRBIAS 9.1kΩ Figure 7. USBRBIAS Connection Table 6. I/O Driver Capability ...

Page 11

... CLKIN 2x 50.0 25.0 50 100 CLKIN (MHz) Internal Clock (MHz) Figure 9. CLKIN, Internal Bus, and Core Clock Ratios MCF5485 Integrated Microprocessor Electrical Characteristics, Rev. 3 Freescale Semiconductor Table 7. Clock Timing Specification Characteristic Min 20 — — Figure 8. Input Clock Timing Diagram Table 8 ...

Page 12

... Chip-select FBCS0 can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing is compatible with common ROM / flash memories. MCF5485 Integrated Microprocessor Electrical Characteristics, Rev Figure 10 Table 9. Reset Timing Specification ...

Page 13

... The FlexBus supports programming an extension of the address hold. Please consult the MCF548X specification manual for more information. 5 These specs are used when the PCIAD[31:0] signals are configured as 32-bit, non-muxed FlexBus address signals. MCF5485 Integrated Microprocessor Electrical Characteristics, Rev. 3 Freescale Semiconductor Table 10. FlexBus AC Timing Specifications Characteristic FlexBus ...

Page 14

... FlexBus CLKIN AD[X:0] AD[31:Y] R/W ALE TSIZ[1:0] FBCSn, BE/BWEn OE TA MCF5485 Integrated Microprocessor Electrical Characteristics, Rev FB1 A[X:0] FB2 A[31:Y] DATA FB4 TSIZ[1:0] FB7 FB6 Figure 11. FlexBus Read Timing FB3 FB5 Freescale Semiconductor ...

Page 15

... SDR mode on write cycles and relative to SDR_DQS on read cycles. The MCF5485 SDRAM controller is a DDR controller with an SDR mode. Because it supports DDR, a DQS pulse must remain supplied to the MCF5485 for each data beat of an SDR read. The MCF5485 accomplishes this by asserting a signal called SDR_DQS during read cycles. During board design, adhere to the following guidelines and specs with regard to the SDR_DQS signal and its usage ...

Page 16

... Because a read cycle in SDR mode continues using the DQS circuit within the MCF548X most critical that the data valid window be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens results in successful SDR reads. The input setup spec is provided as guidance. MCF5485 Integrated Microprocessor Electrical Characteristics, Rev Table 11. SDR Timing Specifications ...

Page 17

... Output Pin) SDRQS (Measured at Input Pin) SDDQS Delayed SDCLK SDDATA form Memories NOTE: Data driven from memories relative to delayed memory clock. MCF5485 Integrated Microprocessor Electrical Characteristics, Rev. 3 Freescale Semiconductor SD3 SD6 COL SD12 WD1 Figure 13. SDR Write Timing SD6 COL tDQS ...

Page 18

... Input Data Hold Relative to DQS (t DD11 DQS falling edge to SDCLK rising (output setup time) (t DD12 DQS falling edge from SDCLK rising (output hold time) (t MCF5485 Integrated Microprocessor Electrical Characteristics, Rev Characteristic 1 Figure 15. DDR Clock Timing Diagram Table 13. DDR Timing Specifications ...

Page 19

... This input skew must include DDR memory output skew and system level board skew (due to routing or other factors). 11 Data input hold is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the first data line becomes invalid. MCF5485 Integrated Microprocessor Electrical Characteristics, Rev. 3 Freescale Semiconductor Min ) 0.9 ...

Page 20

... SDR SDRAM AC Timing Characteristics SDCLK0 SDCLK1 SDCLK0 SDCLK1 SDCSn,SDWE, RAS, CAS DD4 SDADDR, SDBA[1:0] SDDM SDDQS SDDATA MCF5485 Integrated Microprocessor Electrical Characteristics, Rev DD1 DD2 DD5 CMD DD6 ROW COL WD1 WD2 WD3 WD4 Figure 16. DDR Write Timing DD3 DD7 ...

Page 21

... SDADDR, SDBA[1:0] SDDQS SDDATA SDDQS SDDATA 11 PCI Bus The PCI bus on the MCF5485 is PCI 2.2 compliant. The following timing numbers are mostly from the PCI 2.2 spec. Please refer to the PCI 2.2 spec for a more detailed timing analysis. Num — Frequency of Operation P1 Clock Period ( Address, Data, and Command (33< ...

Page 22

... PCI 2.2 spec does not require an output hold time. Although the MCF548X may provide a slight amount of hold not required or guaranteed. 5 PCI 2.2 spec requires zero input hold. 6 These signals are defined at PTP (Point-to-point) in the PCI 2.2 spec. CLKIN Output Valid/Hold Input Setup/Hold MCF5485 Integrated Microprocessor Electrical Characteristics, Rev Characteristic ) ...

Page 23

... M3 RXCLK pulse width high M4 RXCLK pulse width low RXCLK (Input) RXD[3:0] (Inputs) RXDV, RXER Figure 19. MII Receive Signal Timing Diagram MCF5485 Integrated Microprocessor Electrical Characteristics, Rev. 3 Freescale Semiconductor Table 15. MII Receive Signal Timing Characteristic Fast Ethernet AC Timing Specifications Min ...

Page 24

... M11 MDC falling edge to MDIO output valid (max prop delay) M12 MDIO (input) to MDC rising edge setup M13 MDIO (input) to MDC rising edge hold MCF5485 Integrated Microprocessor Electrical Characteristics, Rev Table 16. MII Transmit Signal Timing Characteristic Table 17 ...

Page 25

... Num I1 Start condition hold time I2 Clock low period I3 SCL/SDA rise time (V I4 Data hold time I5 SCL/SDA fall time (V MCF5485 Integrated Microprocessor Electrical Characteristics, Rev. 3 Freescale Semiconductor Characteristic M14 M15 M10 M12 M13 Table 19. General AC Timing Specifications Characteristic C input timing parameters shown in ...

Page 26

... Specified at a nominal 50-pF load. Figure 23 shows timing for the values in I2 SCL I1 SDA MCF5485 Integrated Microprocessor Electrical Characteristics, Rev Characteristic C output timing parameters shown in C Output Timing Specifications Between SCL and SDA Characteristic = 0 2 ...

Page 27

... TRST Setup Time (Negation) to TCLK High 1 MTMOD is expected static signal. Hence not associated with any timing TCLK (Input) TCLK Data Inputs Data Outputs Data Outputs Data Outputs MCF5485 Integrated Microprocessor Electrical Characteristics, Rev. 3 Freescale Semiconductor Table 22. JTAG and Boundary Scan Timing ...

Page 28

... DSCLK and DSI are synchronized internally measured from the synchronized DSCLK input relative to the rising edge of CLKOUT. Figure 28 shows real-time trace timing for the values in PSTCLK PSTDDATA[7:0] MCF5485 Integrated Microprocessor Electrical Characteristics, Rev Figure 26. Test Access Port Timing ...

Page 29

... DSPI_CLK high to DSPI_DOUT invalid. (Output hold) DS4 DSPI_DIN to DSPI_CLK (Input setup) DS5 DSPI_DIN to DSPI_CLK (Input hold) The values in Table 24 correspond to DSPI_CS[3:0] DSPI_CLK DSPI_DOUT DSPI_DIN MCF5485 Integrated Microprocessor Electrical Characteristics, Rev. 3 Freescale Semiconductor Table 23. D5 Current D4 Past Figure 29. BDM Serial Port AC Timing Characteristic Figure 30. ...

Page 30

... Date Number 2.2 August 29, 2005 2.3 August 30, 2005 2.4 December 14, 2005 3 March 1, 2007 MCF5485 Integrated Microprocessor Electrical Characteristics, Rev Characteristic Substantive Changes Table 7: Changed C1 minimum spec from 15. and maximum spec from 33 ns. Table 22: Changed J11 maximum from ns. Table 9: Changed heading maximum from 66 MHz to 50 MHz ...