PT7A6632J PERICOM [Pericom Semiconductor Corporation], PT7A6632J Datasheet - Page 15

• Manufacturer Part Number: PT7A6632J
• Description: PT7A6632 32-Channel HDLC Controller
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

Receive Bit-Level Processor
The block diagram of the Receive Bit-Level Processor is shown
in Figure 12. The receive bit-level processor accept serial data
from the T1/E1 trunk interface, perform HDLC deformat (pro-
cesses flags, abort, deletes zeroes, checks FCS, filters time-fill
bits), or other non-HDLC functions and assemble the processed
bit, including HDLC header, into bytes and sends them into
the external memory. The CPU sets up the channel operation
in a set of linked buffers (referred as receive command/data
buffer) in the external memory. Refer to Figure 26 and 27 in
the Section “External Memory Organization and Definition”.
Timing
Generally, the starting of a data frame received from the T1/E1
trunk interface is not correlated with that of a transmit frame.
As PT7A6632 uses same 8-bit memory bus for data writing
and reading, an elastic buffer is adopted to coordinate the data
access on the bus.
The received data stream is clocked into the elastic buffer by
the RCLK and then clocked out to the Deformat and Rate
Adapt circuit by the TCLK. In this way, the data flow on the
memory bus is simple and coordinated. The data is sampled
and processed in rising edge (SIS = 0) or falling edge (SIS = 1)
of the RCLK. See Figure 14-17.
The RSYNC is used for receive frame synchronization.
Data Rate Adaptation
Reverse process of data rate adaptation of transmission. Illus-
trated in Figure 13.
PT019(05/02)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Figure 12. Block Diagram of Receive Bit-Level Processor
To/From
Manager
Memory
(32 Channels)
Deformat
Fill/Mask
Filter
&
15
PT7A6632 32-Channel HDLC Controller
State/Control Signal
Receive Mornitor
The PT7A6632 monitors the Receive Red Alarm (RRED) in-
put. Once the PT7A6632 detects RRED high, it will stop data
processing in all receive channels and reports by writing the
Status byte. The synchronization will be restored by TMAX
and RSYNC signals.
The PT7A6632 performs data validity check (checks CRC) for
the received data. Once the PT7A6632 finds any errors in the
CRC, the receive interface will stop data processing in current
channel until detects a new HDLC flag byte. The situation is
reported to the external memory. Details are shown in Table 11
for STATUS byte, ABRT, FCER and SHER bits in Section “Ex-
ternal Memory Organization and Definition”.
Hyperchannel
Three standard ISDN hyperchannel options (two for T1, one
for CEPT PCM-30) are available by setting HCS0 and HCS1
as well as T1/CEPT pins. See Table 3 and Figure 11.
The channels can also be randomly grouped into flexible
hyperchannel (with HCS0 HCS1 = 00). A hyperchannel can
contains any number of 32 64kb/s channels. Details is illus-
trated in Section “External Memory Organization and Defini-
tion” and Table 10.
Channel Operation Modes
See receive command buffer in Section “External Memory Or-
ganization and Definition” for details (Figure 27).
Interface
Receive
Elastic
Buffer
RSER
RCLK
RSYNC
RRED
TCLK
Data Sheet
Ver:2