NS16C2552TVA NSC [National Semiconductor], NS16C2552TVA Datasheet

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NS16C2552/NS16C2752 Dual UART with 16-byte/64-byte FIFO’s and Mbit/s Data Rate 1.0 General Description The NS16C2552 and NS16C2752 are dual channel Univer- sal Asynchronous Receiver/Transmitter (DUART). The foot- print and the functions are compatible to the PC16552D, while ...

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General Description ..................................................................................................................................... 1 2.0 Features ....................................................................................................................................................... 1 3.0 System Block Diagram ................................................................................................................................. 4 4.0 Connection Diagrams ................................................................................................................................... 4 5.0 Pin Descriptions ........................................................................................................................................... 5 5.1 PARALLEL BUS INTERFACE ................................................................................................................... 5 5.2 SERIAL IO INTERFACE ............................................................................................................................ 6 5.3 CLOCK AND ...

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AC SPECIFICATIONS ........................................................................................................................... 37 11.0 Timing Diagrams ...................................................................................................................................... 39 12.0 Physical Dimensions ................................................................................................................................ 42 Table of Contents (Continued) 3 www.national.com ...

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... System Block Diagram 4.0 Connection Diagrams 44–PLCC Order Number NS16C2552TVA, NS16C2752TVA; See NS Package Number V44A www.national.com 20204802 48–TQFP Order Number NS16C2552TVS, NS16C2752TVS; See NS Package Number VBC48A 4 20204801 20204830 ...

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Pin Descriptions The NS16C2552/NS16C2752 pins are classified into the following interface categories. • Bus Interface • Serial I/O Interface • Clock and Reset • Power supply and Ground pins Serial channel number ( designated by a ...

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Pin Descriptions Signal PLCC TQFP Name Type Pin # Pin # TXRDY1 O 1 TXRDY2 32 INTR1 O 34 INTR2 17 5.2 SERIAL IO INTERFACE Signal PLCC TQFP Name Type Pin # Pin # SOUT1 SOUT2 ...

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Pin Descriptions (Continued) Signal PLCC TQFP Name Type Pin # Pin # DSR1 DSR2 29 25 DCD1 DCD2 30 26 RI1 RI2 31 27 MF1 MF2 19 ...

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Pin Descriptions 5.3 CLOCK AND RESET Signal PLCC Name Type Pin # XIN I 11 XOUT 5.4 POWER AND GROUND Signal PLCC Name Type Pin # VCC GND ...

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Register Set There are two identical register sets, one for each channel, in the DUART. All register descriptions in this section apply to the register sets in both channels. To clarify the descriptions of transmission and receiving op- erations, ...

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Register Set (Continued) Reg Addr RD/ A2-A0 WR BIT 7 BIT 6 UART 16C550 Compatible Registers (Default Values Upon Reset) RBR R/W Data7 Data6 THR 0x0 Default X X IER R/W CTS Int RTS 0x1 Ena Int Ena Default ...

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Register Set (Continued) TABLE 2. NS16C2552 Register Summary (Continued) Reg Addr RD/ A2-A0 WR BIT 7 BIT 6 BIT 5 DLL R/W DLL DLL 0x0 Bit 7 Bit 6 Default X X DLM R/W DLM DLM 0x1 Bit 7 ...

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Register Set (Continued) Bit Bit Name 7:0 RBR Data 6.2 TRANSMIT HOLDING REGISTER (THR) This register holds the byte-wide transmit data (THR). This is a write-only register. Bit Bit Name 7:0 THR Data 6.3 INTERRUPT ENABLE REGISTER (IER) This ...

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Register Set (Continued) R/W Bit Bit Name Def 0 Rx_DV Int R/W Rx Data Available Interrupt Enable Ena Enable the Received Data Available and FIFO mode time-out interrupt Disable the Received Data Available interrupt ...

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Register Set (Continued) TABLE 8. Interrupt Sources and Clearing (Continued) Interrupt Interrupt Sources Generation Rx Trigger Rx FIFO reached trigger level. RXRDY Time-out in 4-word time plus 12-bit delay time. Timer TXRDY THR empty. MSR Any state change in ...

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Register Set (Continued) Bit R/W Bit Name Def 5:4 Tx FIFO W Transmit FIFO Trigger Level Selection Trig 00 The transmit FIFO trigger threshold selection is only available in NS16C2752. When Level Sel enabled, a transmit interrupt is generated ...

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Register Set (Continued) 6.6 LINE CONTROL REGISTER (LCR) The system programmer specifies the format of the asyn- chronous data communications exchange and sets the Divi- Bit Name R/W Bit Default Def 7 Divisor Latch R/W Ena ...

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Register Set (Continued) Bit Name R/W Bit Default Def 2 Tx/Rx R/W Stop-bit 0 Length Sel 1:0 Tx/Rx Word R/W Length Sel 0 TABLE 10. LCR (0x3) (Continued) Description Tx and Rx Stop-bit Length Select This bit specifies the ...

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Register Set (Continued) 6.7 MODEM CONTROL REGISTER (MCR) This register controls the interface with the MODEM or data set (or a peripheral device emulating a MODEM). There is a R/W Bit Bit Name Def 7 Clk Divider R/W Sel ...

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Register Set (Continued) R/W Bit Bit Name Def 4 Internal R/W Internal Loopback Enable Loopback 0 This bit provides a local loopback feature for diagnostic testing of the associated serial Ena channel. (Refer to Section 7.8 INTERNAL LOOPBACK MODE ...

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Register Set (Continued) 6.8 LINE STATUS REGISTER (LSR) This register provides status information to the CPU con- cerning the data transfer. R/W Bit Bit Name Def 7 Rx FIFO Err THR & TSR R Empty 1 ...

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Register Set (Continued) R/W Bit Bit Name Def 3 Rx Frame R Error Parity R Error Overrun R Error Data R Ready 0 TABLE 12. LSR (0x5) (Continued) Description Framing ...

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Register Set (Continued) 6.9 MODEM STATUS REGISTER (MSR) This register provides the current state of the control lines from the MODEM (or peripheral device) to the CPU. In R/W Bit Bit Name Def 7 DCD Input R Status DCD ...

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Register Set (Continued) 6.10 SCRATCHPAD REGISTER (SCR) This 8-bit Read/Write Register does not control the serial channel in any way intended as a Scratchpad Register to be used by the programmer to hold data temporarily. R/W Bit ...

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Register Set (Continued) 6.12 ALTERNATE FUNCTION REGISTER (AFR) This is a read/write register used to select simultaneous write to both register sets and alter MF pin functions. Bit Name R/W Bit Default Def 7:3 Reserved 2:1 MF Output Sel ...

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Register Set (Continued) 6.14 ENHANCED FEATURE REGISTER (EFR) This register enables the enhanced features of the device. Bit Name R/W Bit Default Def 7 Auto CTS R/W Automatic CTS Flow Control Enable Flow Ctl Enable automatic ...

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Register Set (Continued) Bit Name R/W Bit Default Def 3:0 Software R/W Software Flow Control Select Flow 0 Single character and dual sequential character software flow control is supported. Control Combinations of software flow control can be selected by ...

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Operation and Configuration 7.1 CLOCK INPUT The NS16C2552/2752 has an on-chip oscillator that accepts standard crystal with parallel resonant and fundamental fre- quency. The generated clock is supplied to both UART chan- nels with the capability range from DC ...

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Operation and Configuration (Continued) FIGURE 4. Rx FIFO Mode The RSR operation is described as follows the falling edge of the start bit, an internal timer starts counting at 16X clock. At 8th 16X clock, approximately the ...

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Operation and Configuration (Continued) FIGURE 6. Rx Non-FIFO Mode DMA Mode In the non-FIFO mode, the presence of a received character in RBR causes the assertion of RXRDY at which point DMA transfer can be initiated. Upon transfer completion ...

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Operation and Configuration (Continued) a TXRDY interrupt (IIR[1]=1) when the transmit empty inter- rupt is enabled (IER[1]=1). Writing to THR or reading from IIR deasserts the interrupt. There is a two-character hysteresis in interrupt generation. The host needs to ...

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Operation and Configuration (Continued) FIGURE 11. TXRDY in DMA Mode 0 7.4.3 Transmit Hardware Flow Control CTS is a flow control input used to prevent remote receiver FIFO data overflow. The CTS input is monitored to suspend/ resume the ...

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Operation and Configuration (Continued) 7.7 SLEEP MODE To reduce power consumption, NS16C2552/2752 has a per channel sleep mode when channel is not being used. The sleep mode requires following conditions to be met: • Sleep mode of the respective ...

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Operation and Configuration FIGURE 13. Internal Loopback Functional Diagram (Continued) 33 20204815 www.national.com ...

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Design Notes 8.1 DEBUGGING HINTS Although the UART device is fairly straight forward, there are cases that when device does not behave as expected. The normal trouble shooting steps should include the following. 1. Check power supply voltage and ...

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Design Notes (Continued) 4. The load capacitance of the crystal should match the load capacitance of the oscillator circuitry seen by the crystal. Under the AC conditions, the oscillator load ca- pacitance is a lump sum of parasitic capacitance ...

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Design Notes (Continued) • FCR 0x02 • LCR 0x03.7:0 = temp Features Tx and Rx FIFO sizes Supply voltage Highest baud rate Highest clock input frequency Operating temperature Enhanced Register Set Sleep mode IER[4] Xon, Xoff, and ...

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Absolute Maximum Ratings 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Operating Temperature Storage Temperature All Input or Output Voltages with respect Power Dissipation Symbol ...

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DC and AC Specifications Symbol Parameter t Data Disable Time Strobe Width WR t Write Cycle Delay DY t Data Setup Time DS t Data Hold Time DH t Delay from WR to Output MDO t ...

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Timing Diagrams FIGURE 17. External Clock Input FIGURE 18. Modem Control Timing FIGURE 19. Host Interface Read Timing 39 20204819 20204820 20204821 www.national.com ...

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Timing Diagrams www.national.com (Continued) FIGURE 20. Host Interface Write Timing FIGURE 21. Receiver Timing FIGURE 22. Receiver Timing Non-FIFO Mode FIGURE 23. Receiver Timing FIFO Mode 40 20204822 20204823 20204824 20204825 ...

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Timing Diagrams FIGURE 25. Transmitter Timing Non-FIFO Mode (Continued) FIGURE 24. Transmitter Timing FIGURE 26. Transmitter Timing FIFO Mode 41 20204826 20204827 20204828 www.national.com ...

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... Physical Dimensions www.national.com inches (millimeters) unless otherwise noted 44–PLCC Package Order Number NS16C2552TVA, NS16C2752TVA NS Package Number V44A 48–TQFP Package Order Number NS16C2552TVS, NS16C2752TVS NS Package Number VBC48A 42 ...

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information ...