NS16C2552TVA NSC [National Semiconductor], NS16C2552TVA Datasheet - Page 16

• Manufacturer Part Number: NS16C2552TVA
• Description: Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate
• Manufacturer: NSC [National Semiconductor]

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6.0 Register Set
6.6 LINE CONTROL REGISTER (LCR)
The system programmer specifies the format of the asyn-
chronous data communications exchange and sets the Divi-
Bit
7
6
5
4
3
Divisor Latch
Tx/Rx Parity
Bit Name
Parity Sel
Even/Odd
Parity Sel
Tx Break
Default
Forced
Ena
Ena
Ena
(Continued)
R/W
R/W
R/W
R/W
R/W
R/W
Def
0
0
0
0
0
Divisor Latch Access Bit (DLAB)
This bit must be set (logic 1) to access the Divisor Latches of the Baud Generator
and the Alternate Function Register during a read or write operation. It must be
cleared (logic 0) to access any other register.
1 = Enable access to the Divisor Latches of the Baud Generator and the AFR.
0 = Enable access to other registers (default).
Set Tx Break Enable
This bit is the Break Control bit. It causes a break condition to be transmitted to the
receiving UART. The Break Control bit acts only on SOUT and has no effect on the
transmitter logic.
1 = Serial output (SOUT) is forced to the Spacing State (break state, logic 0).
0 = The break transmission is disabled (default).
Note: This feature enables the CPU to alert a terminal in a computer communication
system. If the following sequence is followed, no erroneous or extraneous character
will be transmitted because of the break.
1. Load an all 0s, pad character, in response to THRE.
2. Set break after the next THRE.
3. Wait for the transmitter to be idle, (Transmitter Empty TEMT = 1), and clear break
when normal transmission has to be restored.
During the break, the transmitter can be used as a character timer to establish the
break duration.
During the break state, any word left in THR will be shifted out of the register but
blocked by SOUT as forced to break state. This word will be lost.
Tx and Rx Forced Parity Select
When parity is enabled, this bit selects the forced parity format.
Tx and Rx Even/Odd Parity Select
This bit is only effective when LCR[3]=1. This bit selects even or odd parity format.
1 = Odd parity is transmitted or checked.
0 = Even parity is transmitted or checked (default).
Tx and Rx Parity Enable
This bit enables parity generation.
1 = A parity is generated during the data transmission. The receiver checks for parity
error of the data received.
0 = No parity (default).
LCR[5]
1
1
0
0
X
TABLE 10. LCR (0x3)
LCR[4]
1
0
1
0
X
16
sor Latch Access bit via the Line Control Register (LCR).
This is a read and write register.
LCR[3]
1
1
1
1
0
Description
Force parity to space = 0
Force parity to mark = 1
Even parity
Odd parity
No parity
Parity Select