NS16C2552TVA NSC [National Semiconductor], NS16C2552TVA Datasheet - Page 13

• Manufacturer Part Number: NS16C2552TVA
• Description: Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate
• Manufacturer: NSC [National Semiconductor]

6.0 Register Set
Bit
LSR
6.4 INTERRUPT IDENTIFICATION REGISTER (IIR)
In order to provide minimum software overhead during data
word transfers, each serial channel of the DUART prioritizes
interrupts into seven levels and records these levels in the
Interrupt Identification Register. The seven levels of interrupt
conditions are listed in Table 7. When the CPU reads the IIR,
Generation
0
Priority
Interrupt
Level
Bit
7:6
3:1
5
4
0
1
2
3
4
5
6
7
-
Rx_DV Int
Bit Name
Ena
INT Src 3:1
FIFOs Ena
Bit Name
INT Src 5
INT Src 4
INT Src 0
Any bit is set in LSR[4:1] (Break Interrupt,
Framing, Rx parity, or overrun error).
5
0
0
0
0
0
0
1
0
R/W
R/W
Def
0
(Continued)
4
0
0
0
0
0
1
0
0
IIR Register Status Bits
Interrupt Sources
Rx Data Available Interrupt Enable
1 = Enable the Received Data Available and FIFO mode time-out interrupt.
0 = Disable the Received Data Available interrupt (default).
R/W
Def
000
00
R
R
R
R
R
0
0
1
3
0
1
0
0
0
0
0
0
TABLE 7. Interrupt Source and Priority Level
TABLE 8. Interrupt Sources and Clearing
TABLE 5. IER (0x1) (Continued)
FIFO Enable Status (FCR 0x2.0)
2’b11 = Tx and Rx FIFOs enabled.
2’b00 = Tx and Rx FIFOs disabled (default).
RTS/CTS Interrupt Status
1 = RTS or CTS changed state from low to high.
0 = No change on RTS or CTS from low to high (default).
Xoff or Special Character Interrupt Status
1 = Receiver detected Xoff or special character.
0 = No Xoff character match (default).
Interrupt Source Status
These three bits indicates the source of a pending interrupt. Refer to Table 7 for
interrupt source and priority.
Interrupt Status
1 = No interrupt is pending (default).
0 = An interrupt is pending and the IIR content may be used as a pointer for the
interrupt service routine.
2
1
1
1
0
0
0
0
0
TABLE 6. IIR (0x2)
1
1
0
0
1
0
0
0
0
13
the associated DUART serial channel freezes all interrupts
and indicates the highest priority pending interrupt to the
CPU. While this CPU access is occurring, the associated
DUART serial channel records new interrupts, but does not
change its current indication until the access is complete.
Table 6 shows the contents of the IIR.
0
0
0
0
0
0
0
0
1
Read LSR register. (Interrupt flags and tags are not
cleared until the character(s) that generated the
interrupt(s) has/have been emptied or cleared.)
LSR
RXRDY (Receive data time-out)
RXRDY (Receive data ready)
TXRDY (Transmit data ready)
MSR (Modem Status Register)
RXRDY (Received Xoff or special character)
CTS, RTS change state from low to high
None (default)
Description
Description
Interrupt Clearing
Interrupt Source
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