A3PE1500-1FG896 ACTEL [Actel Corporation], A3PE1500-1FG896 Datasheet - Page 7

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A3PE1500-1FG896

Manufacturer Part Number
A3PE1500-1FG896
Description
ProASIC3E Flash Family FPGAs
Manufacturer
ACTEL [Actel Corporation]
Datasheet
Figure 1-1 • ProASIC3E Device Architecture Overview
ISP AES Decryption
Advanced Architecture
The proprietary ProASIC3E architecture provides granularity comparable to standard-cell ASICs. The
ProASIC3E device consists of five distinct and programmable architectural features
page
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input
logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate
flash switch interconnections. The versatility of the ProASIC3E core tile as either a three-input
lookup table (LUT) equivalent or as a D-flip-flop/latch with enable allows for efficient use of the
FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation
architecture Flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy.
Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable
interconnect programming. Maximum core utilization is possible for virtually any design.
In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V)
programming of ProASIC3E devices via an IEEE 1532 JTAG interface.
3):
FPGA VersaTiles
Dedicated FlashROM
Dedicated SRAM/FIFO memory
Extensive CCCs and PLLs
Pro I/O structure
User Nonvolatile
FlashROM
v1.0
Charge Pumps
CCC
RAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
Pro I/Os
VersaTile
RAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
ProASIC3E Flash Family FPGAs
(Figure 1-1 on
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