A3PE1500-1FG896 ACTEL [Actel Corporation], A3PE1500-1FG896 Datasheet - Page 80

• Manufacturer Part Number: A3PE1500-1FG896
• Description: ProASIC3E Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

ProASIC3E DC and Switching Characteristics
Clock Conditioning Circuits
Table 2-94 • ProASIC3E CCC/PLL Specification
2 -6 8
Parameter
Clock Conditioning Circuitry Input Frequency f
Clock Conditioning Circuitry Output Frequency f
Delay Increments in Programmable Delay Blocks
Serial Clock (SCLK) for Dynamic PLL
Number of Programmable Values in Each
Programmable Delay Block
Input Period Jitter
CCC Output Peak-to-Peak Period Jitter F
Acquisition Time
Tracking Jitter
Output Duty Cycle
Delay Range in Block: Programmable Delay 1
Delay Range in Block: Programmable Delay 2
Delay Range in Block: Fixed Delay
Notes:
1. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific
2. This delay is a function of voltage and temperature. See
3. T
4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL
junction temperature and voltage supply levels, refer to
input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by
the period jitter parameter.
J
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 250 MHz
250 MHz to 350 MHz
= 25°C, V
CCC Electrical Specifications
Timing Characteristics
4
CC
= 1.5 V.
1, 2
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
1
CCC_OUT
2, 3
2, 3
IN_CCC
2, 3
OUT_CCC
v1.2
Minimum
Network
1 Global
Table 2-6 on page 2-5
Table 2-6 on page 2-5
0.50%
1.00%
1.75%
2.50%
0.025
Used
0.75
48.5
1.5
0.6
Max Peak-to-Peak Period Jitter
Typical
160
2.2
for derating values.
for deratings.
Maximum
Networks
3 Global
0.70%
1.20%
2.00%
5.60%
Used
51.5
5.56
5.56
350
350
125
300
1.5
6.0
1.6
0.8
32
Units
MHz
MHz
MHz
ms
ps
ns
µs
ns
ns
%
ns
ns
ns