GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 25

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

1.5 Output Timing Signals
Table 1-3: Output Timing Signals
Signal Name
H Sync
H Blanking
Description
The H Sync signal has a leading edge at the start of the horizontal sync pulse.
Its length is determined by the selected video standard (see
according to custom timing parameters programmed in the host interface (see
Section 3.10 on page
The width of the H Sync output pulse is determined by the selected video
standard.
video and graphics standard recognized by the GS4911B/GS4910B. Custom
video timing parameters may also be programmed in the host interface to
define a unique H Sync width (see
In Genlock mode the leading edge of the output H Sync signal is nominally
simultaneous with the half amplitude point of the reference HSYNC input. This
timing may be offset using the Genlock Offset registers beginning at address
1Bh of the host interface (see
By default, after system reset, the polarity of the H Sync signal output will be
active LOW. The polarity may be selected as active HIGH by programming the
Polarity register at address 56h of the host interface (see
page
The H Blanking signal is used to indicate the portion of the video line not
containing active video data.
The H Blanking signal will be LOW (default polarity) for the portion of the video
line containing valid video samples. The signal will be LOW at the first valid
pixel of the line, and HIGH after the last valid pixel of the line.
The H Blanking signal remains HIGH throughout the horizontal blanking period.
The width of this signal will be determined by the selected video standard (see
Table
interface (see
When in Genlock mode, the output H Blanking signal will be phase locked to the
reference HSYNC input. This timing may be offset using the Genlock Offset
registers beginning at address 1Bh of the host interface (see
page
The default polarity of this signal may be inverted by programming the Polarity
register at address 56h of the host interface (see
79).
37).
1-2), or according to custom timing parameters programmed in the host
Table 1-3
TIMING_OUT_1 to TIMING_OUT_8. The user may output any of the signals listed
below on each pin by programming the Output_Select registers beginning at
address 43h of the host interface.
s
36655 - 2
Table 1-2
Section 3.10 on page
lists the H Sync width (in clocks) of each pre-programmed
describes the output timing signals available to the user via pins
74).
April 2006
Section 3.2.1.1 on page
Section 3.10 on page
74).
Section 3.12.3 on page
37).
74).
Section 3.12.3 on
GS4911B/GS4910B Data Sheet
Table
Section 3.2.1.1 on
1-2), or
79).
Default Output Pin
TIMING_OUT_1
TIMING_OUT_2
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