GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 98

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

Table 3-13: Configuration and Status Registers (Continued)
Register Name
H_Start_1
H_Stop_1
V_Start_1
V_Stop_1
Address
56h
56h
56h
57h
58h
59h
59h
5Ah
5Ah
36655 - 2
Bit
2
1
0
15-0
15-0
15
14-0
15
14-0
April 2006
Reserved. Set this bit to zero when writing to 5Ah.
Description
V_Sync - set this bit HIGH to invert the polarity of the V
Sync timing output signal.
By default, the V Sync signal is active LOW.
Reference:
H_Blanking - set this bit HIGH to invert the polarity of
the H Blanking timing output signal.
By default, the H Blanking signal will be LOW for the
portion of the video line containing valid video samples.
Reference:
H_Sync - set this bit HIGH to invert the polarity of the H
Sync timing output signal.
By default, the H Sync signal is active LOW.
Reference:
The value programmed in this register indicates the
pixel start point for the leading edge of the
user-programmed H Sync signal USER1_H.
NOTE: The value programmed in this register must be
less than the value programmed in H_Stop_1.
Reference:
The value programmed in this register indicates the
pixel end point for the trailing edge of the
user-programmed H Sync signal USER1_H.
NOTE: The value programmed in this register must not
exceed the maximum number of clock periods per line
of the outgoing standard.
Reference:
Reserved. Set this bit to zero when writing to 59h.
The value programmed in this register indicates the start
line number of the leading edge of the
user-programmed V Sync signal USER1_V. For
interlaced output standards, this value corresponds to
the odd field number.
NOTE: The value programmed in this register must be
less than the value programmed in V_Stop_1.
Reference:
The value programmed in this register indicates the end
line number of the trailing edge of the user-programmed
V Sync signal USER1_V. For interlaced output
standards, this value corresponds to the odd field
number.
NOTE: The value programmed in this register must not
exceed the maximum number of lines per field of the
outgoing standard.
Reference:
Table 1-3
Table 1-3
Table 1-3
Section 3.8.3 on page 69
Section 3.8.3 on page 69
Section 3.8.3 on page 69
Section 3.8.3 on page 69
GS4911B/GS4910B Data Sheet
R/W
R/W
R/W
R/W
R/W
R/W
–
R/W
–
R/W
Default
0
0
0
0
0
–
0
–
0
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