GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 90

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

Table 3-13: Configuration and Status Registers (Continued)
Register Name
Audio_Control
(GS4911B only)
ASR_SEL[2:0]
(GS4911B only)
Address
31h
31h
31h
31h
31h
31h
31h
31h
32h
32h
36655 - 2
Bit
15-10
9-7
6
5
4-3
2
1
0
15-3
2-0
April 2006
Description
Reserved. Set these bits to zero when writing to 31h.
AFS_Reset_Window - These bits may be used to adjust
the value by which the audio clock counters are allowed
to drift from the output AFS pulse.
The encoding scheme for this register is shown in
Table
NOTE: The default setting of this register will provide a
reset window that is sufficient for most standards. To
maintain correct audio clock frequencies for some
VESA standards, the reset window may have to be
increased from its default setting. In this case, set the
value of this register to 1XX. See
Reference:
Update_Custom_A_Clock - this bit is used to update the
custom audio clock parameters programmed in
registers 33h to 36h of the host interface. All non-zero
parameters in these registers will be updated via a LOW
to HIGH transition on this bit.
Enable_384fs - set this bit HIGH to enable the 384fs
and 192fs audio clock outputs. This must be set in
addition to registers 3Fh to 41h.
NOTE: If this bit is HIGH, then a 512fs audio clock will
have a 33% duty cycle when fs = 96kHz.
Reference:
Reserved. Set these bits to zero when writing to 31h.
Host_ASR_SEL - set this bit HIGH to select the audio
sample rate using register 32h instead of the external
ASR_SEL[2:0] pins.
The external ASR_SEL[2:0] pins will be ignored, but
should not be left floating.
Reference:
AFS_F_Pulse - set this bit to 1 to stretch the AFS pulse
duration from 1 line to 1 field.
Reference:
AFS_Reset_Disable - set this bit HIGH to disable the
10FID input reference pin from resetting the output AFS
pulse. If this bit is set HIGH, the output AFS pulse will
free-run or may be reset using register 1Ah. The
external 10FID pin should not be left floating.
Reference:
Reserved. Set these bits to zero when writing to 32h.
Replaces the external ASR_SEL[2:0] pins when
Host_ASR_Select (bit 2 of address 31h) is HIGH.
The default setting of this register corresponds to an
audio sample rate of 48kHz.
Reference:
3-9.
Section 3.7.2 on page 63
Section 3.7.2 on page 63
Section 3.7.2 on page 63
Section 3.8.2 on page 68
Section 3.8.2 on page 68
Section 3.7.2 on page 63
GS4911B/GS4910B Data Sheet
Table
3-9.
R/W
–
R/W
R/W
R/W
–
R/W
R/W
R/W
–
R/W
Default
–
010b
0
0
–
0
0
0
–
011b
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