24LC04 MicrochipTechnology, 24LC04 Datasheet - Page 4

• Manufacturer Part Number: 24LC04
• Description: 4K/8K2.5VI2CSerialEEPROMs
• Manufacturer: MicrochipTechnology

24LC04B/08B
2.0
The 24LC04B/08B supports a Bi-directional 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24LC04B/08B
works as slave. Both, master and slave can operate as
transmitter or receiver but the master device deter-
mines which mode is activated.
3.0
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is
• During data transfer, the data line must remain
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Both data and clock lines remain HIGH.
3.2
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
FIGURE 3-1:
DS21051E-page 4
SCL
not busy.
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
SDA
(A)
FUNCTIONAL DESCRIPTION
BUS CHARACTERISTICS
Bus not Busy (A)
Start Data Transfer (B)
Stop Data Transfer (C)
CONDITION
START
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
ACKNOWLEDGE
ADDRESS OR
VALID
(D)
TO CHANGE
ALLOWED
DATA
3.4
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
3.5
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse.
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
Note:
Data Valid (D)
Acknowledge
The 24LC04B/08B does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
(D)
1996 Microchip Technology Inc.
CONDITION
STOP
(C)
(A)
Of