LP2996LQ National Semiconductor, LP2996LQ Datasheet - Page 8

• Manufacturer Part Number: LP2996LQ
• Description: DDR Termination Regulator
• Manufacturer: National Semiconductor

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Block Diagram
Description
The LP2996 is a linear bus termination regulator designed to
meet the JEDEC requirements of SSTL-2. The output, V
capable of sinking and sourcing current while regulating the
output voltage equal to VDDQ / 2. The output stage has
been designed to maintain excellent load regulation while
preventing shoot through. The LP2996 also incorporates two
distinct power rails that separates the analog circuitry from
the power output stage. This allows a split rail approach to
be utilized to decrease internal power dissipation. It also
permits the LP2996 to provide a termination solution for the
next generation of DDR-SDRAM memory (DDRII). The
LP2996 can also be used to provide a termination voltage for
other logic schemes such as SSTL-3 or HSTL.
Series Stub Termination Logic (SSTL) was created to im-
prove signal integrity of the data transmission across the
memory bus. This termination scheme is essential to prevent
data error from signal reflections while transmitting at high
frequencies encountered with DDR-SDRAM. The most com-
mon form of termination is Class II single parallel termina-
tion. This involves one R
S
series resistor from the chipset to
TT
is
8
the memory and one R
for R
to scale the current requirements from the LP2996. This
implementation can be seen below in Figure 1.
S
and R
FIGURE 1. SSTL-Termination Scheme
T
are 25 Ohms, although these can be changed
T
termination resistor. Typical values
20057505
20057506