24AA04 MicrochipTechnology, 24AA04 Datasheet - Page 5

• Manufacturer Part Number: 24AA04
• Description: 4K/8K1.8VI2CSerialEEPROMs
• Manufacturer: MicrochipTechnology

3.6
A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a four bit control code, for the 24AA04/08
this is set as 1010 binary for read and write operations.
The next three bits of the control byte are the block
select bits (B2, B1, B0). B2 is a don't care for both the
24AA04 and 24AA08; B1 is a don't care for the 24AA04.
They are used by the master device to select which of
the two or four 256 word blocks of memory are to be
accessed. These bits are in effect the most significant
bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24AA04/08 monitors
the SDA bus checking the device type identifier being
transmitted, upon a 1010 code the slave device outputs
an acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24AA04/08 will select a
read or write operation.
FIGURE 3-2:
FIGURE 4-1:
FIGURE 4-2:
SDA LINE
Operation
BUS ACTIVITY
MASTER
BUS ACTIVITY
SDA LINE
1996 Microchip Technology Inc.
BUS ACTIVITY
MASTER
BUS ACTIVITY
Read
Write
Device Addressing
X = don't care, B1 is don't care for 24AA04
1
START
0
Control
Code
1010
1010
CONTROL BYTE
ALLOCATION
BYTE WRITE
PAGE WRITE
SLAVE ADDRESS
S
S
T
A
R
T
1
S
S
T
A
R
T
0
Block Address
Block Address
CONTROL
Block Select
CONTROL
BYTE
X
READ/WRITE
BYTE
B1
R/W
B0
A
C
K
ADDRESS (n)
A
R/W
WORD
1
0
A
C
K
A
C
K
ADDRESS
WORD
4.0
4.1
Following the start condition from the master, the
device code (4 bits), the block address (3 bits), and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted by
the master is the word address and will be written into
the address pointer of the 24AA04/08. After receiving
another acknowledge signal from the 24AA04/08 the
master device will transmit the data word to be written
into the addressed memory location. The 24AA04/08
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and dur-
ing this time the 24AA04/08 will not generate acknowl-
edge signals (Figure 4-1).
4.2
The write control byte, word address, and the first data
byte are transmitted to the 24AA04/08 in the same way
as in a byte write. But instead of generating a stop con-
dition, the master transmits up to 16 data bytes to the
24AA04/08 which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).
DATA n
WRITE OPERATION
Byte Write
Page Write
A
C
K
A
C
K
DATA n + 1
24AA04/08
DATA
A
C
K
DATA n + 15
DS21053E-page 5
A
C
K
P
S
T
O
P
A
C
K
S
T
O
P
P