24LC65-IP MicrochipTechnology, 24LC65-IP Datasheet
24LC65-IP
Related parts for 24LC65-IP
24LC65-IP Summary of contents
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... SDA Vcc Vss blocks. Functional address lines allow the connection eight 24LC65's on the same bus for up to 512K bits contiguous EEPROM memory. Advanced CMOS technology makes this device ideal for low-power non- volatile code and data applications. The 24LC65 is available in the standard 8-pin plastic DIP and 8-pin surface mount SOIC package ...
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... ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* V ...................................................................................7.0V CC All inputs and outputs w.r.t. V ............... -0. Storage temperature ...................................... -65˚C to+150˚C Ambient temp. with power applied ................ -65˚C to +125˚C Soldering temperature of leads (10 seconds) ............. +300˚C ESD protection on all pins *Notice: Stresses above those listed under “Maximum Ratings” ...
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... Schmitt trigger inputs which provide improved T HIGH DAT SU DAT 24LC65 Units Remarks kHz (Note 1) ns (Note 1) ns After this period the first clock pulse is generated ns Only relevant for repeated START condi- tion ...
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... NOT generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24LC65) must leave the data line HIGH to enable the master to generate the STOP condition. (D) ...
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... A control byte is the first byte received following the start condition from the master device. The control byte consists of a four bit control code, for the 24LC65 this is set as 1010 binary for read and write operations. The next three bits of the control byte are the device select bits (A2, A1, A0) ...
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... FIGURE 4-2: PAGE WRITE (FOR CACHE WRITE, SEE FIGURE 8- BUS CONTROL A ADDRESS (1) ACTIVITY BYTE R MASTER T SDA LINE BUS C ACTIVITY: K FIGURE 4-3: CURRENT ADDRESS READ S T BUS ACTIVITY A MASTER SDA LINE BUS ACTIVITY FIGURE 4-4: RANDOM READ S T WORD CONTROL ...
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... The device select bits A2, A1, A0 can be used to expand the contiguous address space for up to 512K bits by adding up to eight 24LC65's on the same bus. In this case, software can use A0 of the control byte as address bit A13 address bit A14, and A2 as address bit A15 ...
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... Security Options The 24LC65 has a sophisticated mechanism for write-protecting portions of the array. This write protect function is programmable and allows the user to protect 0-15 contiguous 4K blocks. The user sets the security option by sending to the device the starting block num- ber for the protected region and the number of blocks to be protected ...
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... PIN DESCRIPTIONS 8.1 A0, A1, A2 Chip Address Inputs The A0..A2 inputs are used by the 24LC65 for multiple device operation and conform to the two-wire bus stan- dard. The levels applied to these pins define the address block occupied by the device in the address map. A particular device is selected by transmitting the corresponding bits (A2, A1, A0) in the control byte (Figure 3-2 and Figure 8-1) ...
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... FIGURE 8-1: CONTROL SEQUENCE BIT ASSIGNMENTS Control Byte Address Byte R Slave Device Address Select Bits Security Read S t Acknowledges from Device ...
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... Page 0 of cache written to page 3 of array. Write cycle is executed after every page is written. • • • byte 2 byte 3 byte 4 byte 7 page 3 24LC65 cache page 7 • • • bytes 56-63 array row n • • • page 7 array row • • • ...
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... Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. 24LC65 – /P Package: Temperature Range: Device: AMERICAS Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. ...