HM6264 Hitachi Semiconductor, HM6264 Datasheet - Page 12

• Manufacturer Part Number: HM6264
• Description: 64 k SRAM (8-kword x 8-bit)
• Manufacturer: Hitachi Semiconductor

HM6264B Series
Low V
Parameter
V
Data retention current
Chip deselect to data
retention time
Operation recovery time
Notes: 1. Reference data at Ta = 25 C.
Low V
Low V
CC
for data retention
CC
CC
2. 10 A max at Ta = 0 to + 40 C.
3. t
4. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls
4.5 V
0.4 V
4.5 V
2.2 V
CC
CS2
CS1
V
V
V
V
0 V
Data Retention Timing Waveform (1) (CS1 Controlled)
Data Retention Timing Waveform (2) (CS2 Controlled)
0 V
CC
DR
CC
DR
data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance
state. If CS1 controls data retention mode, CS2 must be CS2
V. The other input levels (address, WE, OE, I/O) can be in the high impedance state.
Data Retention Characteristics (Ta = 0 to +70 C)
RC
= read cycle time.
t
CDR
Symbol
V
I
t
t
CCDR
CDR
R
DR
t
CDR
Min
2.0
—
0
t
RC
Data retention mode
*3
CS1
Data retention mode
Typ
—
1
—
—
*1
CS2
V
*1
CC
– 0.2 V
Max
—
25
—
—
0.2 V
*2
Unit
V
ns
ns
A
Test conditions
CS1
CS2
V
CS1
or 0 V
See retention waveform
CC
V
CC
t
= 3.0 V, 0 V
R
– 0.2 V or 0 V
V
V
V
CC
CS2
CC
CC
t
R
–0.2 V or CS2
–0.2 V,
–0.2 V, CS2
0.2 V
*4
Vin
CS2
V
CC
V
CC
0.2 V
0.2
–0.2 V