AK5354VT Asahi Kasei Microsystems, AK5354VT Datasheet - Page 14

• Manufacturer Part Number: AK5354VT
• Description: LOW POWER 20 BIT ADC WITH PGA
• Manufacturer: Asahi Kasei Microsystems

ASAHI KASEI
Input Analog PGA Control
MS0054-E-01
Addr
03H
ZEIP:
IPGA6-0: Input Analog PGA. 97 levels. 00H=MUTE.
Register Name
Input Analog PGA Control
RESET
Select IPGA zero crossing operation (0: Disable, 1: Enable)
detection or timeout independently.
the operation which is the same as the case of ZEIP = “0”.
In the timeout cycle, it is possible to set in ZTM1-0 bit.
When ZTM1-0 is “11”, timeout cycle is 2048/fs = 46.4ms (@fs=44.kHz).
ON/OFF of zero crossing detection can be controlled by ZEIP bit.
Inhibits writing at PM0 = “0”.
Writing to IPGA value at ZEIP = “1”, IPGA value of L/R channels changes by zero crossing
When ZEIP is “0”, IPGA changes immediately. When PM1 is “0”, ZEIP is ignored and IPGA does
DATA
5FH
5EH
0FH
0EH
60H
28H
27H
19H
18H
17H
16H
11H
10H
05H
04H
03H
02H
01H
00H
ZEIP
D7
0
Table 4. Input Gain Setting
IPGA6
GAIN(dB)
MUTE
D6
+28.0
+27.5
+27.0
-10.0
-15.0
-16.0
-18.0
-20.0
-38.0
-40.0
-44.0
-48.0
-52.0
+0.0
-0.5
-7.5
-8.0
-9.0
- 14 -
IPGA5
D5
0.5dB
Step
1dB
2dB
4dB
IPGA4
D4
00H (MUTE)
Level
73
12
IPGA3
8
3
1
D3
IPGA2
D2
IPGA1
D1
[AK5354]
2001/01
IPGA0
D0