AK4516AVF Asahi Kasei Microsystems, AK4516AVF Datasheet

no-image

AK4516AVF

Manufacturer Part Number
AK4516AVF
Description
3V 16BIT ADC&DAC WITH BUILT-IN PGA
Manufacturer
Asahi Kasei Microsystems
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AK4516AVF
Manufacturer:
ROCKWELL
Quantity:
2 899
Part Number:
AK4516AVF
Manufacturer:
AKM
Quantity:
20 000
ASAHI KASEI
M0026-E-00
1 . Resolution: 16 bits
2 . Recording Function
3 . Playback Function
4 . Analog-Through Mode
5 . Power Management
6 . ADC Input (Including the PGA)
7 . DAC Output
8 . Master Clock: 256fs/384fs
9 . Audio Data Format
10 . Ta: -20 85 C
11 . Power Supply: 2.5 3.6V
12 . Power Dissipation: 18mA
13 . 24pinVSOP (0.65mm Pitch)
• Digital De-emphasis Filter(tc=50/15us, fs=32kHz, 44.1kHz, 48kHz)
Analog Input PGA (Programmable Gain Amp)
Peak-Meter Output
Overflow Flag Output
Auto Limitter Circuit
Auto Recovery Circuit
HPF(fc=3.4Hz) for offset cancel
Single-ended Input
Input Level: 1.7Vpp (=0.57 VA, VA=3V)
THD+N: -85dB
DR,S/N: 90dB
Single-ended Output
Output Level: 1.8Vpp (=0.6 VA, VA=3V, R
Frequency Response: ±0.5dB( 20kHz)
THD+N: -86dB
DR,S/N: 90dB
ADC:
DAC:
16bit, MSB first,
MSB justified, IIS, LSB justified(only BICK=64fs correspondent)
16bit, MSB first,
MSB justified, IIS, MSB justified
FEATURE
- 1 -
3V 16bit ADC&DAC with built-in PGA
L
10k )
AK4516A
[AK4516A]

Related parts for AK4516AVF

AK4516AVF Summary of contents

Page 1

ASAHI KASEI 1 . Resolution: 16 bits 2 . Recording Function Analog Input PGA (Programmable Gain Amp) Peak-Meter Output Overflow Flag Output Auto Limitter Circuit Auto Recovery Circuit HPF(fc=3.4Hz) for offset cancel 3 . Playback Function • Digital De-emphasis Filter(tc=50/15us, ...

Page 2

ASAHI KASEI M0026-E- [AK4516A] 1998/08 ...

Page 3

... ASAHI KASEI Ordering Guide AK4516AVF AKD4516A Pin Layout M0026-E-00 C -20 +85 24pin VSOP(0.65mm Pitch) Evaluation Board - 3 - [AK4516A] 1998/08 ...

Page 4

ASAHI KASEI No. Pin Name I/O 1 AGND - Analog Ground pin Analog Power Supply Pin, +3V 3 RIN1 I Rch #1 input pin 4 LIN1 I Lch #1 input pin 5 RIN2 I Rch #2 input ...

Page 5

ASAHI KASEI (AGND,DGND=0V; Note 1 ) Parameter Power Supplies: Analog Digital VD-VA Input Current (Any pin except supplies.) Analog Input Voltage LIN1,LIN2,RIN1,RIN2 Digital Input Voltage Ambient Temperature Storage Temperature Note 1 . All Voltage with respect to ground. RECOMMENDED OPERATING ...

Page 6

ASAHI KASEI C (Ta=25 ; VA,VD=3.0V; fs=44.1kHz; Signal Frequency=1kHz; Measurement Frequency=10Hz 20kHz ; S/(N+D), DR, S/N are specification toward full scale.signal; Unless otherwise specified) Parameter Input PGA(IPGA) Characteristics: Input Voltage(LIN1,LIN2,RIN1,RIN2=0.57xVA)(Note2 ) Input Resistance Step Size MIC +28dB -8dB -8dB -32dB ...

Page 7

ASAHI KASEI (Ta= VA,VD=2.5 3.6V; fs=44.1kHz; DEM bit="0") Parameter ADC Digital Filter (LPF): Passband (Note 6 ) ±0.1dB -0.55dB -1.2dB Stopband Passband Ripple Stopband Attenuation Group Delay (Note 7 ) Group Delay Distortion ADC Digital Filter (HPF): Frequency ...

Page 8

ASAHI KASEI C (Ta=25 ; VA,VD=2.5 3.6V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout=-400uA) Low-Level Output Voltage (Iout=400uA) Input Leakage Current (Ta= VA,VD=2.5 3.6V; C =20pF) L Parameter Control Clock Frequency Master Clock (MCLK) ...

Page 9

ASAHI KASEI Timing Diagram M0026-E-00 Data Input Timing in WRITE - 9 - [AK4516A] 1998/08 ...

Page 10

ASAHI KASEI M0026-E-00 Reset Timing - 10 - [AK4516A] 1998/08 ...

Page 11

ASAHI KASEI System Clock The clocks which are required to operate are MCLK(256fs/384fs), LRCK(fs), BCLK(32fs ). The master clock (MCLK) should be synchronized with LRCK but the phase is free of care. The MCLK can be input 256fs or 384fs. ...

Page 12

ASAHI KASEI Audio Serial Interface Format Data is shifted in/out the SDTI/SDTO pins using BCLK and LRCK inputs. Four serial data are selected by the DIF0 and DIF1 pins as shown in Table all modes, the serial ...

Page 13

ASAHI KASEI M0026-E-00 Figure 4. Audio Data Timing (No. [AK4516A] 1998/08 ...

Page 14

ASAHI KASEI Control Register R/W Timing The data on the 4 wires serial interface consists of op-code(3bit), address(LSB-first, 5bit) and control data (LSB-first, 8bit). The transmitting data is output to each bit by " " of CCLK, the receiving data ...

Page 15

ASAHI KASEI INIT: Initializing. At this time, ZFIPL and ZFIPR are "0". When these flags becomes "1", INIT process has completed. PD: Power-down state. ADC is output "0", analog output of DAC goes floating. INIT-1: Initializing all registers. INIT-2: Initializing ...

Page 16

ASAHI KASEI Operation mode explanation The AK4516A can perform the limitter operation and the recovery operation automatically. There are three operation modes. 1. Manual Mode The manual mode is used when the AK4516A mode is changed (for example, when the ...

Page 17

ASAHI KASEI 2. Semi-auto Mode The semi-auto mode is the mode that uses the AK4516A auto limitter function, and the recovery operation is processed DSP etc. During the semi-auto mode, writing to the following registers from uP ...

Page 18

ASAHI KASEI Figure 8 Register set-up sequence at Semi-auto mode M0026-E- [AK4516A] 1998/08 ...

Page 19

ASAHI KASEI 3. Full-auto Mode The full-auto mode is done automatically by the auto limitter and the auto recovery function of the AK4516A. However, writing to the register is needed to enable these functions. During the full-auto mode, writing to ...

Page 20

ASAHI KASEI Figure 10 . Registers set-up sequence at Full-auto mode M0026-E- [AK4516A] 1998/08 ...

Page 21

ASAHI KASEI Register Map Addr Register Name 00H Input Select 01H Mode Control 1 02H Mode Control 2 03H Zero Cross & Timer Control 04H Peak Hold Low Byte Lch 05H Peak Hold High Byte Lch 06H Peak Hold Low ...

Page 22

ASAHI KASEI Mode Control 1 Addr Register Name 01H Mode Control 1 R/W RESET PM3-0: Power Management (0: Power Down, 1:Power Up) PM0: Mixer, PGA input, Auto Limitter and Auto Recovery power control. PM1: Power control of ADC PM2: Power ...

Page 23

ASAHI KASEI M0026-E-00 Figure 11 . Power Management - 23 - [AK4516A] 1998/08 ...

Page 24

ASAHI KASEI Mode Control 2 Addr Register Name 02H Mode Control 2 R/W RESET MONO1-0:Monaural Mixing 00: Stereo (RESET) 01: (L+R)/2 10: LL 11: RR DIF1-0: Select Audio Serial Interface Format The data is all 2's complement, MSB first. No. ...

Page 25

ASAHI KASEI Zero Cross & Timer Control Addr Register Name 03H Zero Cross & Timer Control R/W RESET LRGA: Selects the method of writing to IPGA 0: Independent data can be written to IPGA and IPGR. 1: Common data can ...

Page 26

ASAHI KASEI LTM1-0:Zero crossing timeout(ZELM="1") or Update period(ZELM="0") at the auto limitter mode LTM1 LTM0 Zero crossing timeout(ZELM="1" 129/ 258/ 516/ 1032/fs Table 6 . Zero crossing timeout or Update period at ...

Page 27

ASAHI KASEI Overflow Status Addr Register Name 08H Overflow Status R/W RESET ZFIPR: Rch IPGA zero crossing detection flag. ZFIPL: Lch IPGA zero crossing detection flag. At writing operation when ZENM is "1", this flag becomes "0" ...

Page 28

ASAHI KASEI LOF2-0: Overflow Flag of Lch Overflow flag includes 3bit. Max value of overflow is held. These bits are reset to ( reading These bits are reset on the following any conditions. PD ...

Page 29

ASAHI KASEI Auto Limitter Control During the auto limitter operation, when either Lch or Rch exceed auto limitter detection level (LMTH1-0), IPGA value is attenuated by auto limitter ATT step (LMAT1-0) automatically. Then the IPGA value is changed commonly for ...

Page 30

ASAHI KASEI LMAT2-0: Auto Limitter ATT Step During the auto limitter operation, when either Lch or Rch exceeds the auto limitter detection level set by LMTH1-0, the number of steps attenuated from current IPGA value is set. For example, when ...

Page 31

ASAHI KASEI IPGL6-0: Lch Input Analog PGA. IPGR6-0: Rch Input Analog PGA. ON/OFF of zero crossing detection is controlled by ZENM/ZELM bits. DATA 68H 67H 66H : RESET 30H 2FH : 21H 20H 1FH 1EH : 09H 08H 07H 06H ...

Page 32

ASAHI KASEI Auto Recovery Control Auto recovery operation starts after completing auto limitter operation (LCDET="1") at LMTE=RCVE="1". IPGA gain increases automatically by this operation up to the set reference level(REF6-0). Then the IPGA value is set for L/R commonly. Either ...

Page 33

ASAHI KASEI Figure 12 . Auto Recovery Operation (LMAT=RATT = 1 Step, ZENM=ZELM="1") 1 After completing the auto limitter operation, the auto recovery operation wait for only a period set by WTM1-0. If the auto limitter operation is not occurred ...

Page 34

ASAHI KASEI Addr Register Name 0DH Auto Recovery Control 2 R/W RESET REF6-0: Set the Reference value at Auto Recovery Operation During the auto recovery operation, when IPGA value becomes the reference value set by REF6-0, the gain of the ...

Page 35

ASAHI KASEI Figure 13 shows the system connection example. An evaluation board [AKD4516A] is available which demonstrates the optimum layout, power supply arrangement and measurement results. NOTE: - LRCK=fs, SCLK - Power supply lines of VA and VD should be ...

Page 36

ASAHI KASEI 1. Grounding and Power Supply Decoupling The AK4516A requires careful attenuation to power supply and grounding arrangements. When VA and VD are supplied separately, VA should not be the higher voltage than VD not ...

Page 37

ASAHI KASEI 24pin VSOP (Unit: mm) NOTE: Dimension “*” does not include mold flash. Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: M0026-E-00 PACKAGE Epoxy Cu Solder plate - 37 - [AK4516A] 1998/08 ...

Page 38

ASAHI KASEI M0026-E-00 MARKING Contents of AAXXXX AA: Lot# XXXX: Date Code - 38 - [AK4516A] 1998/08 ...

Page 39

... IMPORTANT NOTICE These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein ...

Related keywords