AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 113

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

11
10
MERR
RINT
This bit is always read/write ac-
cessible. MISS is cleared by the
host by writing a 1. Writing a 0
has no effect. MISS is cleared by
H_RESET, S_RESET, or by set-
ting the STOP bit.
set by the Am79C978 controller
when it requests the use of the
system interface bus by asserting
REQ and has not received GNT
assertion after a programmable
length of time. The length of time
in microseconds before MERR is
asserted will depend upon the
setting of the Bus Timeout Regis-
ter (CSR100). The default setting
of CSR100 will give a MERR after
153.6 ms of bus latency.
When MERR is set, INTA is as-
serted if IENA is 1 and the mask
bit MERRM (CSR3, bit 11) is 0.
MERR assertion will set the ERR
bit, regardless of the settings of
IENA and MERRM.
This bit is always read/write ac-
cessible. MERR is cleared by the
host by writing a 1. Writing a 0
has no effect. MERR is cleared
by H_RESET, S_RESET, or by
setting the STOP bit.
Am79C978 controller after the
last descriptor of a receive frame
has been update by writing a 0 to
the ownership bit (OWN). RINT
may also be set when the first de-
scriptor of a receive frame has
been updated by writing a 0 to the
ownership bit if the LAPPEN bit of
CSR3 has been set to a 1.
When RINT is set, INTA is assert-
ed if IENA is 1 and the mask bit
RINTM (CSR3, bit 10) is 0.
This bit is always read/write ac-
cessible. RINT is cleared by the
host by writing a 1. Writing a 0
has no effect. RINT is cleared by
H_RESET, S_RESET, or by set-
ting the STOP bit.
Memory Error. Memory Error is
Receive Interrupt is set by the
Am79C978
9
8
7
TINT
IDON
INTR
When TINT is set, INTA is assert-
ed if IENA is 1 and the mask bit
TINTM (CSR3, bit 9) is 0.
TINT will not be set if TINTOKD
(CSR5, bit 15) is set to 1 and the
transmission was successful.
This bit is always read/write ac-
cessible. TINT is cleared by the
host by writing a 1. Writing a 0
has no effect. TINT is cleared by
H_RESET, S_RESET, or by set-
ting the STOP bit.
When IDON is set, INTA is as-
serted if IENA is 1 and the mask
bit IDONM (CSR3, bit 8) is 0.
This bit is always read/write ac-
cessible. IDON is cleared by the
host by writing a 1. Writing a 0
has no effect. IDON is cleared by
H_RESET, S_RESET, or by set-
ting the STOP bit.
Am79C978 controller after the
OWN bit in the last descriptor of a
transmit frame has been cleared
to indicate the frame has been
sent or an error occurred in the
transmission.
Am79C978 controller after the
initialization sequence has com-
pleted. When IDON is set, the
Am79C978 controller has read
the initialization block from mem-
ory.
Interrupt Flag indicates that one
or more following interrupt caus-
ing conditions has occurred:
EXDINT, IDON, MERR, MISS,
MFCO, RCVCCO, RINT, SINT,
TINT, TXSTRT, UINT, STINT,
MREINT, MCCINT, MIIPDTINT,
MAPINT and the associated
mask or enable bit is pro-
grammed to allow the event to
cause an interrupt. If IENA is set
to 1 and INTR is set, INTA will be
active. When INTR is set by SINT
or SLPINT, INTA will be active in-
dependent of the state of IENA.
Transmit Interrupt is set by the
Initialization Done is set by the
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