K4S641632C Samsung semiconductor, K4S641632C Datasheet - Page 28

• Manufacturer Part Number: K4S641632C
• Description: 1M x 16Bit x 4 Banks Synchronous DRAM
• Manufacturer: Samsung semiconductor

DQ
CLOCK
K4S641632C
Read & Write Cycle at Same Bank @Burst Length=4
A
ADDR
DQM
10
CKE
RAS
CAS
WE
BA
BA
/AP
CS
CL=2
CL=3
0
1
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.
0
Row Active
(A-Bank)
ELECTRONICS
Ra
Ra
1
2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data
3. Access time from Row active command. t
4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
is available after Row precharge. Last valid output will be Hi-Z(t
tRCD
2
*Note 3
tRAC
3
(A-Bank)
*Note 3
tRAC
Read
Ca
4
5
Qa0
tSAC
6
tRC
Qa1
Qa0
tOH
tSAC
*Note 1
7
Qa2
Qa1
CC
tOH
*Note 2
8
*(t
Precharge
(A-Bank)
RCD
Qa3
Qa2
9
+ CAS latency - 1) + t
HIGH
Qa3
tSHZ
10
*Note 4
tSHZ
SHZ
11
Row Active
(A-Bank)
) after the clcok.
Rb
*Note 4
Rb
12
SAC
13
(A-Bank)
Write
Db0
Db0
Cb
14
Db1
Db1
15
Db2
Db2
16
CMOS SDRAM
Db3
Db3
17
Precharge
(A-Bank)
18
tRDL
tRDL
: Don't care
19