K4S56163LC Samsung semiconductor, K4S56163LC Datasheet - Page 2

• Manufacturer Part Number: K4S56163LC
• Description: 16Mx16 Mobile SDRAM 54CSP
• Manufacturer: Samsung semiconductor

FUNCTIONAL BLOCK DIAGRAM
K4S56163LC-R(B)F/R
4M x 16Bit x 4 Banks Mobile SDRAM in 54CSP
FEATURES
• 2.5V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
• Burst read single-bit write operation.
• Special Function Support.
• DQM for masking.
• Auto refresh.
• 64ms refresh period (8K cycle).
• Commercial Temperature Operation (-25 C ~ 70 C).
• 54balls CSP (-RXXX - Pb, -BXXX - Pb Free).
clock.
-. Burst length (1, 2, 4, 8 & Full page).
-. CAS latency (1 & 2 & 3).
-. Burst type (Sequential & Interleave).
-. PASR (Partial Array Self Refresh).
-. TCSR (Temperature Compensated Self Refresh).
ADD
CLK
LCKE
* Samsung Electronics reserves the right to change products or specification without notice.
CLK
LRAS
CKE
Bank Select
LCBR
CS
LWE
RAS
Timing Register
LCAS
CAS
Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabri-
cated with SAMSUNG's high performance CMOS technology. Syn-
chronous design allows precise cycle control with the use of
system clock and I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst length
and programmable latencies allow the same device to be useful for
a variety of high bandwidth, high performance memory system
applications.
ORDERING INFORMATION
-R(B)R ; Super Low Power, Operating Temperature ; -25 C~85 C.
-R(B)F ; Low Power, Operating Temperature ; -25 C~85 C.
Notes :
1. In case of 40MHz Frequency, CL1 can be supported.
2. In case of 33MHz Frequency, CL1 can be supported.
The K4S56163LC is 268,435,456 bits synchronous high data rate
K4S56163LC-R(B)F/R1H
K4S56163LC-R(B)F/R75
K4S56163LC-R(B)F/R1L
K4S56163LC-R(B)F/R15
GENERAL DESCRIPTION
Latency & Burst Length
Programming Register
WE
Data Input Register
Column Decoder
4M x 16
4M x 16
4M x 16
4M x 16
Part No.
L(U)DQM
LWCBR
66MHz(CL=2/3)
105MHz(CL=3)
133MHz(CL=3)
105MHz(CL=2)
105MHz(CL=2)
Max Freq.
CMOS SDRAM
Rev. 1.4 Dec. 2002
LDQM
*1
*2
Interface Package
LVCMOS
LWE
LDQM
DQi
(Pb Free)
54 CSP
Pb