K4S643232H-TC/L50 Samsung semiconductor, K4S643232H-TC/L50 Datasheet
K4S643232H-TC/L50
Related parts for K4S643232H-TC/L50
K4S643232H-TC/L50 Summary of contents
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... SDRAM 64Mb H-die (x32) 64Mb H-die (x32) SDRAM Specification *Samsung Electronics reserves the right to change products or specification without notice. Revision 1.4 August 2004 - 1 - CMOS SDRAM Rev. 1.4 August 2004 ...
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... SDRAM 64Mb H-die (x32) Revision History Revision 0.0 (June, 2003) - Target spec First release. Revision 0.1 (July, 2003) - Delete speed 4.5ns. Revision 0.2 (September, 2003) - Preliminary spec release. Revision 1.0 (November, 2003) - Final spec release. Revision 1.1 (December, 2003) - Corrected typo. Revision 1.2 (December, 2003) - Modified load cap 50pF -> 30pF & Typo. ...
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... I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Ordering Information Part No. K4S643232H-TC/L70 K4S643232H-TC/L60 K4S643232H-TC/L55 K4S643232H-TC/L50 Organization Orgainization Max Freq. 143MHz(CL=3) 166MHz(CL=3) 2Mb x 32 ...
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... SDRAM 64Mb H-die (x32) Package Physical Dimension #86 #1 0.10 MAX 0.004 0. 0.024 #44 #43 22.62 MAX 0.891 22.22 ± 0.10 ± 0.004 0.875 0.008 +0.07 0.20 0.50 -0.03 +0.003 0.0197 0.0079 -0.001 86Pin TSOP(II) Package Dimension - 4 - CMOS SDRAM 0.25 TYP 0.010 +0.075 0.125 -0.035 +0.003 0.005 -0.001 0.21 ± 0.05 ± 0.10 1.00 1.20 MAX ± 0.002 ± ...
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... SDRAM 64Mb H-die (x32) FUNCTIONAL BLOCK DIAGRAM Bank Select CLK ADD LCKE LRAS LCBR CLK CKE Data Input Register 512K x 32 512K x 32 512K x 32 512K x 32 Column Decoder Latency & Burst Length Programming Register LWE LCAS Timing Register CS RAS CAS ...
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... SDRAM 64Mb H-die (x32) PIN CONFIGURATION (Top view DQM0 A10/AP DQM2 DQ16 V DQ17 DQ18 V DQ19 DQ20 V DQ21 DQ22 V DQ23 DQ0 DDQ DQ1 4 83 DQ2 SSQ DQ3 7 80 DQ4 DDQ DQ5 10 77 ...
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... SDRAM 64Mb H-die (x32) PIN FUNCTION DESCRIPTION Pin Name CLK System clock CS Chip select CKE Clock enable Address 0 10 BA0,1 Bank select address RAS Row address strobe CAS Column address strobe WE Write enable DQM0 ~ 3 Data input/output mask DQ ~ Data input/output 0 31 ...
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... SDRAM 64Mb H-die (x32) ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. ...
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... Operating Current I CC4 (Burst Mode) Refresh Current I CC5 Self Refresh Current I CC6 Notes : 1. Unless otherwise notes, Input level is CMOS(V 2. Measured with outputs open. 3. Refresh period is 64ms. 4. K4S643232H-TC 5. K4S643232H- 70°C A Test Condition Burst Length =1 ≥ t ≥ (min), t (min 0mA CKE ≤ ...
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... SDRAM 64Mb H-die (x32) AC OPERATING TEST CONDITIONS Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Output 870Ω (Fig output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) ...
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... SDRAM 64Mb H-die (x32) AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter CAS Latency=3 CLK cycle time CAS Latency=2 CAS Latency=3 CLK to valid output delay CAS Latency=2 Output data hold time CAS Latency=3 CLK high pulse width CAS Latency=2 CAS Latency=3 CLK low ...
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... MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. ...